Acknowledgments

We are indebted to Professor Wayne Wolf of the electrical engineering department at Princeton University and Richard Rubinstein for their detailed review of the manuscript, constructive criticism, and suggestions of information to be added.

In addition we would like to thank the following people and companies:

The staff of Prentice Hall, especially Bernard Goodwin, for his support of this project
Ken Schmidt for reviewing the chapter on low power
Ron Sailors for reviewing parts of the book
Farshid Tabrizi and Munir Ahmed of Ammocore Technology Inc.
Michel Courtoy, vice president of marketing at Silicon Prespective, Inc. (A Cadence Company)
Plato Design Systems (A Cadence Company)
Fujitsu Microelectronics of America
Sequence Design, Inc.
OCP-IP association
The staff of BooksCraft, Inc., for their help in producing the book

Farzad Nekoogar
Faranak Nekoogar

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Chapter 1. Introduction

Section 1.1. Introduction

Section 1.2. Voice Over IP SOC

Section 1.3. Intellectual Property

Section 1.4. SOC Design Challenges

Section 1.5. Design Methodology

Section 1.6. Summary

Section 1.7. References

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1.1 Introduction

The ASIC (Application Specific Integrated Circuit) and SOC (System on a Chip) abbreviations are used every day in the integrated circuit design industry. However, there are still a lot of ambiguities when differentiating SOCs from traditional ASICs. Some designers define SOCs as complex integrated circuits with more than one on-chip processor. Many use the term when describing ICs that have more than 10 million gates plus on-chip processors. Still others define it as ICs that contain soft and hard functional blocks as well as digital and analog components . Let's give our own definition here.

An SOC is a system on an IC that integrates software and hardware Intellectual Property (IP) using more than one design methodology for the purpose of defining the functionality and behavior of the proposed system. In most cases, the designed system is application specific. Typical applications can be found in the consumer, networking, communications, and other segments of the electronics industry. Voice over Internet Protocol (VoIP) is a good example of an emerging market where SOCs are widely designed. Figure 1.1 shows an example of a typical gateway VoIP system-on-a-chip diagram.

Figure 1.1. A Typical Gateway SOC Architecture

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1.2 Voice Over IP SOC

A gateway VoIP SOC is a device used for functions such as vocoders, echo cancellation, data/fax modems, and VoIP protocols. Currently, there are a number of these devices available from several vendors ; typically these devices differ from each other by the type of functions and voice-processing algorithms they support.

In this example, we define the major blocks required to support carrier-class voice processing. The SOC can vary depending on the particular I/O and voice-processing requirements of the mediation gateway architecture. Major units for this SOC are as follows .

Host/PCI

The host interface is for control, code download, monitoring, and in some cases data transport. This host interface could be either a microprocessor-specific interface or a generic system-bus interface such as PCI.

Microprocessor Interface A synchronous processor interface, such as a 32-bit synchronous Motorola 68000 or Intel 960 style interface operating at 33MHz with interrupt support, allows the SOC to interface to most processors with minimal glue logic. This interface usually supports multiplexed data and addresses to reduce the number of I/Os on the SOC. The SOC also supports interrupt generation in order to notify the CPU of external events.
PCI Interface The SOC may have a PCI-compliant interface for communication with external processors and resources. The PCI interface would support bus Target (Slave) and Initiator (Master) functions and DMA, but would not require an arbiter. This interface also provides access to shared memory.

External Memory Controller

The external memory controller supports industry-standard inexpensive fast memory such as SDRAM. This memory is used to store code and data for processing elements within the SOC. Depending on the actual SOC architecture and fabrication process, the memory interface could require support for one 32-bit SDRAM module, two 16-bit modules operating at up to 133MHz.

Flash Memory Interface

A standard parallel flash port for access to boot programs, configuration data, and programs is available and accessible upon system reset.

Packet Interface

The packet interface can be Ethernet or Utopia.

Ethernet A standard 10/100BT Ethernet MII or RMII interface may be useful in cases where both compression and packetization are performed in the SOC. In such architectures, IP packets may be transported within a system using Ethernet as the physical transport layer.
Utopia An industry standard, Utopia level 2 interface is useful for interfacing to system fabrics that use ATM as a physical transport. This interface supports connections to ATM 155Mbit/s physical-layer interfaces.

TDM Interface

The TDM interface is the downstream interface to PSTN TDM streams. These are uncompressed voice channels of 64Kbit/s A-LAW/ µ-LAW voice that is delivered to the SOC for compression and forwarding to the packet network. The SOC interfaces directly with legacy TDM device interfaces such as the ECTF H.100/H.110 standard serial interface.

ECTF H.100/H.110 H.100/H.110 is a standard TDM interface for legacy telephony equipment. H.100/H.110 allows the transport of up to 4096 simplex channels of voice or data on one connector or ribbon cable. This voice traffic may come from a WAN interface board, chip, or any other voice-processing device in the carrier systems described above. H.100 defines a mezzanine connection that can interface to other H.100 devices or to legacy MVIP/SCSA devices.

SOC Extension Bus

The SOC extension bus is required to load balance the system and to provide a unified host interface for access.

Voice/Tone Processing Unit

The voice/tone processing unit consists of multiple DSP cores that perform the following functions:

Code excited linear prediction (CELP)
Pulse code modulation (PCM)
Echo cancellation
Silence suppression
Voice activity detector (VAD)
Tone detection/generation
Dual-tone multifrequency (DTMF)

Packet Processing Unit

The packet-processing unit consists of several packet processors that process the voice and signaling packets that are ready for transmission. This unit performs the following functions:

ATM Adaptation Layer 1 (AAL1)
ATM Adaptation Layer 2 (AAL2)
User Datagram Protocol (UDP)
Transfer Control Protocol (TCP)

We will spend more time on this gateway SOC in Chapter 3. Let's look at another SOC example. Figure 1.2 shows an overview diagram of a set-top-box (STB) SOC.

Figure 1.2. Set-Top-Box SOC

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The major blocks in Figure 1.2 and their functions are listed below:

Video processing unit (MPEG-2 codec)
Digital signal processing (DSP) for AC3 audio processing
CPU for control and transport of streams
Modulation unit such as quadrature phase shift keying (QPSK) for satellite and quadrature amplitude modulation (QAM) for cable inputs
Utopia for cable modem interface
Memory controller such as SDRAM controller
I/O controller
Display controller

A more detailed example of an STB is presented in Section 3.4.

In many SOC designs, you will find the following characteristics:

Hierarchical architecture
Hierarchical methods for physical design (placement and routing) and timing analysis
On-chip interconnect
Standard core-to- core communication protocols
Hardware/Software codesign/verification
Reusable infrastructure