5.5. Upcoming PCI Bus Technologies

This section provides a glimpse of the newest PCI specifications, PCI-X 2.0, and PCI Express.

5.5.1 PCI-X 2.0

Figure 5-16 shows how bus technologies have evolved over time.

Figure 5-16. Evolution of bus technologies.

The PCI-X 2.0 specification was released in July 2002. PCI-X 2.0 has four times the bandwidth of PCI-X without increasing its pin count. It is backward compatible with the hardware and software of PCI and PCI-X. Figure 5-16 shows how aggregate bandwidth has increased with the introduction of new bus technologies.

The PCI-X 2.0 specification defines two new versions of PCI-X add-in cards.

The PCI-X 266 runs at speeds up to 266MT/s, enabling sustainable PCI bandwidth of more than 2.1GB/s.

The PCI-X 533 runs at speeds up to 533MT/s, enabling bandwidth of more than 4.2GB/s.

Such throughput rates are more than sufficient to handle current applications and also support future high-bandwidth add-in card connections to 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, Serial Attached SCSI, Serial ATA (SATA), InfiniBand, RAID, and cluster interconnects for servers and workstations.

PCI-X 2.0 leverages the protocol enhancements used in the widely adopted PCI-X 1.0 specification, such as byte counts and split transactions, enabling maximum operational efficiency with host bridges, PCI-to-PCI bridges, and main memory.

The PCI-X 2.0 specification also incorporates error checking and correction, ensuring end-to-end data integrity. Additionally, the bus per slot provided with PCI-X 2.0 delivers excellent fault isolation and improved performance guarantees for advanced levels of reliability.

PCI-X 2.0 is fully backward compatible with previous generations of PCI, which means that system board designers and system designers can immediately deploy products that accommodate existing PCI cards, and at the same time support present and future low-cost, high-bandwidth PCI-X 2.0 devices. In addition, PCI-X 2.0 adapter cards will be able to plug into any PCI slot and operate at the maximum speed of that slot.

5.5.2 PCI Express

The PCI Express specification was also released in July 2002. PCI Express defines a packetized protocol and a load/store architecture. Its layered architecture enables attachment to copper, optical, or emerging physical signaling media. It can be used for chip-to-chip and add-in card applications to provide connectivity for adapter cards, as a graphics I/O attach point for increased graphics bandwidth, and as an attach point to other interconnects such as InfiniBand.

PCI Express is a fully serial interconnect with links that use multiple, point-to-point connections called lanes. Its initial speed of 2.5Gb/s per direction provides two unidirectional 200MB/s communication channels that represent roughly three times the speed of classic PCI. By adding more lanes, bandwidth can be easily scaled.

PCI Express is designed with long-term scalability in mind. Key features include the following:

• Higher bandwidth per pin

• Low overhead

• Low latency

• Embedded clock architecture

Embedded clock timing and differential signaling enables PCI Express performance to scale to the limits of copper signaling, which are expected to be in the 10 to 15Gb/s range for high-volume copper technology.

The embedded clock architecture requires fewer pins than parallel architectures, which simplifies routing. This helps minimize costs and allows wider flexibility for component, motherboard, adapter, and system design. Fewer signals also means that systems can be designed using less board space and smaller connectors, which, in turn, supports smaller and more innovative form factors.

PCI Express is compatible with the current PCI software environment. PCI Express eventually might replace PCI, but InfiniBand architecture and PCI Express will be able to coexist because the primary focus of each is complementary:

• The focus of the InfiniBand architecture is on shared I/O in a multicomputer environment using a robust message-passing architecture.

• The focus of PCI Express is cost-effective local I/O, using a load/store architecture.

PCI Express is building on the electrical layer and silicon building blocks of the InfiniBand architecture. This is a key enabler toward future convergence of the two I/O architectures.

I/O requirements will be driven beyond the current capabilities and cost-effective scalability potential of the PCI bus by technology advances, including the following:

• Processor speeds in excess of 10GHz

• Faster memory speeds

• Higher-speed graphics

• 1Gb and 10Gb LANs

PCI Express is important to developers because it creates a high-performance, highly scalable, general-purpose I/O architecture. Additionally, it will be designed to serve as a long-term, general-purpose I/O interconnect to meet the requirements of desktop, mobile, server, communications, embedded, and other emerging and future applications.