4. Introducing `Makefile' s

4.1 Targets and dependencies

The make program attempts to bring a target up to date by bring all of the target's dependencies up to date. These dependencies may have further dependencies. Thus, a potentially complex dependency graph forms when processing a typical `Makefile' . From a simple `Makefile' that looks like this:

all: foo

foo: foo.o bar.o baz.o

.c.o:
        $(CC) $(CFLAGS) -c $< -o $@

.l.c:
        $(LEX) $< && mv lex.yy.c $@

We can draw a dependency graph that looks like this:

all
                
               foo
                
        .-------+-------.
       /                \
    foo.o     bar.o     baz.o
                        
    foo.c     bar.c     baz.c
                          
                        baz.l

Unless the `Makefile' contains a directive to make , all targets are assumed to be filename and rules must be written to create these files or somehow bring them up to date.

When leaf nodes are found in the dependency graph, the `Makefile' must include a set of shell commands to bring the dependent up to date with the dependency. Much to the chagrin of many make users, up to date means the dependent has a more recent timestamp than the target. Moreover, each of these shell commands are run in their own sub-shell and, unless the `Makefile' instructs make otherwise , each command must exit with an exit code of 0 to indicate success.

Target rules can be written which are executed unconditionally. This is achieved by specifying that the target has no dependents. A simple rule which should be familiar to most users is:

clean:
	-rm *.o core

4.2 Makefile syntax

`Makefile' s have a rather particular syntax that can trouble new users. There are many implementations of make , some of which provide non-portable extensions. An abridged description of the syntax follows which, for portability, may be stricter than you may be used to.

Comments start with a `#' and continue until the end of line. They may appear anywhere except in command sequences--if they do, they will be interpreted by the shell running the command. The following `Makefile' shows three individual targets with dependencies on each:

target1:  dep1 dep2 ... depN
<tab>	  cmd1
<tab>	  cmd2
<tab>	  ...
<tab>	  cmdN

target2:  dep4 dep5
<tab>	  cmd1
<tab>	  cmd2

dep4 dep5:
<tab>	  cmd1

Target rules start at the beginning of a line and are followed by a colon. Following the colon is a whitespace separated list of dependencies. A series of lines follow which contain shell commands to be run by a sub-shell (the default is the Bourne shell). Each of these lines must be prefixed by a horizontal tab character. This is the most common mistake made by new make users.

These commands may be prefixed by an `@' character to prevent make from echoing the command line prior to executing it. They may also optionally be prefixed by a `-' character to allow the rule to continue if the command returns a non-zero exit code. The combination of both characters is permitted.