Chapter 1. Introduction to HyperTransport

This Chapter

This chapter discusses some of the motivations leading to the development of HyperTransport. It reviews some of the attributes that limit the ability of older generation I/O buses to keep pace with the increasing demands of new applications and advances in processor and memory technologies. The chapter then summarizes the key features behind the improved performance of HT over earlier buses.

The Next Chapter

The next chapter provides an overview of HT architecture, including the primary elements of HT technology and the relationship between them. The chapter describes the general features, capabilities, and limitations of HT and introduces the terminology and concepts necessary for in-depth discussions of the various HT topics in subsequent chapters.