6.7 CORE SHDSL Framer (PMS-TC)

The structure of the SHDSL core frame is based on the superframe structure of HDSL2 as described in Chapter 4. This section briefly describes the SHDSL core frame per Recommendation G.991.2.

Figure 6.19 shows the core SHDSL physical layer superframe. The nominal frame period ( T _frame ) is 6 msec. There are four blocks for payload data bits identified as PB1 “PB4. Because the line bit rate is variable, the number of bits in an SHDSL superframe will depend on the payload bit rate.

Figure 6.19. SHDSL core frame structure.

graphics/06fig19.gif

There are also five subblocks allocated for overhead bits labeled as OH1 “OH4 and block SB (stuff bits). OH1 has 16 bits, OH2 “OH4 each has 10 bits, and the SB block has nominally 2 bits, but the size may vary between 0 and 4 bits. Note, however, that for the nominal superframe there are nominally 48 bits in the overhead channel.

The following is a summary of the overhead bit definitions.

OH1 (16 bits) : This block contains a 14-bit frame synchronization word (FSW). The definition of the FSW is vendor specific. During preactivation , the transmitter forwards its preferred FSW to the far-end receiver via the specified exchange protocol. The remaining two bits are fixed indicator bits. The first indicator bit identifies a loss of signal from an application interface. The second indicator identifies segment anomaly, which is generally a cyclic redundancy check (CRC) error determined on an incoming SHDSL frame.
OH2 (10 bits):
- Bits 1 “4 : EOC bits #1 “4
- Bits 5 and 6 : crc-1 & crc-2
- Bit 7 : Fixed indicator bit #3, which defines the power status of the local power supply in the customer premises SHDSL unit (STU-R)
- Bit 8 : Stuff bit ID #1 (first copy). This bit is used when the pass-thru timing mode is enabled. Otherwise, this is a spare bit.
- Bits 9 and 10 : EOC bits 5 and 6.
OH2 (12 bits):
- Bits 1 “4 : EOC bits #7 “10
- Bits 5 and 6 : bits crc-3 and crc-4
- Bit 7 : Fixed indicator bit #4 that defines segment defect. A segment defect indicates a loss of synchronization on the incoming SHDSL frame. Perhaps a regenerator has lost synchronization, and therefore the regenerated data is unavailable.
- Bits 8 “9 : EOC bits #11 and 12
- Bit 10 : Stuff bit ID #2 (second copy). This bit is used when the pass-thru timing mode is enabled. Otherwise, this is a spare bit.
OH3 (12 bits):
- Bits 1 “4 : EOC bits #13 “17
- Bits 5 and 6 : bits crc-5 and crc-6
- Bits 7 “10 : EOC bits #18 “20
SB (0 or 4 bits):
- Bits 1 “2 : Vendor depend definition.
- Either 0 or 4 : These stuff bits are not present during synchronous timing mode where the line clock is frequency locked to the payload clock.

The six CRC bits are used for performance monitoring of the subscriber line. The six CRC check bits, crc-1 “crc-6, are those associated with the contents of the previous SHDSL superframe. The CRC is computed over all of the bits in the superframe except for the 14 sync word bits, the 6 CRC bits, and the nominally 2 SBs; hence, the data message contains 4K + 26 bits. The message polynomial is constructed such that first CRC computable bit is the coefficient of the term x ^4K+25 , and the last bit is the coefficient of the term x . The polynomial is then multiplied by a factor of x ⁶ , and the result is divided (modulo-2) by the generator polynomial x ⁶ + x + 1. The coefficients of the remainder polynomial are used in the order of occurrence as the ordered set of check bits crc-1 “crc-6. In the remainder polynomial, the coefficient of the term x ⁵ is crc-1 and that for the term x is crc-6.

The embedded operations channel has 24 bits allocated in a 6 msec frame. This corresponds to a 4 kb/s clear data communications channel. This channel is used to pass operations and maintenance information between the CO and CP HDSL2 transceiver units.

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