6.8 Timing Configurations
| There are three mode timing operation defined in G.991.2, namely
Each of these timing modes is described below. Figure 6.20 shows the transceiver-timing configuration for the plesiochronous timing mode. This is the timing configuration used for classic HDSL operation. The transceiver line clock, that is, the transmit symbol clock, operates independent (free running) from the payload data clock. For this application, the payload timing reference needs to be transferred end to end. In this timing mode, the pulse stuffing operations are enabled, and the payload data clocks (i.e., Tx_Clock signals) are passed end to end. Note that due to the pulse stuffing and deleting operations, recovered payload data clock (Rx_Clock) will have some residual jitter. The amount of residual jitter depends on the circuit implementation. Figure 6.20. Plesiochronous timing mode. In this timing mode, the central office unit (STU-C) serves as the master timing source for the line (symbol) clock, being that it is derived from a local oscillator. The customer premises unit (STU-R) derives the line (symbol) clock from the received line signal and uses this recovered clock at the transmit line (symbol) clock for the STU-R. This timing configuration at the customer premises unit is referred to as loop timing. The network timing reference mode is similar to that of the plesiochronous timing mode. The exception is that the transmit symbol clock at the central office unit (STU-C) is derived from a local network timing reference as opposed to a local oscillator. In this mode of operation, the pulse stuffing operations are enabled as well. This mode of operation should allow for better residual output jitter on the recovered payload data clock because the timing sources are more closely matched. The third timing mode operation is the synchronous timing mode, which is shown in Figure 6.21. In this mode of operation, the transmit symbol clock of the central office unit is frequency locked to timing source of the transmit data signal. Because the payload clock and the line clock are frequency locked, the stuff/delete operations in the core frame are disabled. Note that as in the other timing modes, the STU-R operates in the loop timing mode. Figure 6.21. Synchronous timing mode. |
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