Control transfer instructions

We talked a little bit about control transfer instructions in Chapter 16 on the SPARC assembly language, specifically regarding the delay instruction. Now let's talk about them in more detail.

Control transfer instructions perform the following tasks :

• Test and branch based on the values of the PSR icc fields (integer condition codes)

• Test and branch based on the values of the floating-point unit's condition codes

• Test and branch based on the values of the coprocessor unit's condition codes

• Unconditional branches

• Test and trap based on the values of the PSR icc fields

• Orderly return from a trap

We will start with the test and branch or conditional branch instructions. They all have the same general instruction format, as shown here:

  instruction{,a} label  

{,a} represents an option that each conditional branch instruction offers and refers to the annul bit. If , a is appended to the instruction, the annul bit is set. We will talk about the annul bit again later on.

Branch on integer condition codes instructions

The next table shows the conditional test and branch instructions for the integer unit. The third column shows which conditions the PSR icc bits must satisfy in order for the branch to be taken. As a reminder, the icc bits are:

• Condition N, n egative result occurred

• Condition Z, result was z ero

• Condition V, o v erflow occurred

• Condition C, bit 31 was c arried or borrowed

Here are the branch on integer condition codes instructions:

Table B-12. Branch on integer condition codes instructions

Instruction Syntax	Operation	icc Test
ba{,a} label	Branch always to label
bn{,a} label	Branch never to label
bne{,a} label	Branch on not equal	not Z
be{,a} label	Branch on equal	Z
bg{,a} label	Branch on greater	not (Z or (N xor V))
ble{,a} label	Branch on less or equal	Z or (N xor V)
bge{,a} label	Branch on greater or equal	not (N xor V)
bl{,a} label	Branch on less	N xor V
bgu{,a} label	Branch on greater unsigned	not (C or Z)
bleu{,a} label	Branch on less or equal unsigned	C or Z
bcc{,a} label	Branch on carry clear (greater or equal unsigned)	not C
bcs{,a} label	Branch on carry set (less unsigned)	C
bpos{,a} label	Branch on positive	not N
bneg{,a} label	Branch on negative	N
bvc{,a} label	Branch on overflow clear	not V
bvs{,a} label	Branch on overflow set	V

Here is a snippet of assembly code that demonstrates how a branch instruction might be used.

 main+0x34:      ld      [%l4 - 0x8], %l0  main+0x38:      subcc   %l0, 0x6, %g0  main+0x3c:      bne     main + 0x5c  main+0x40:      nop  main+0x44:      ld      [%fp - 0x8], %l0 

A value is read in from memory and placed into local register %l0 .

Using the "subtract & modify icc " instruction, we subtract 6 from the value in %l0 . No result is stored because the dreg or destination register is the /dev/null of registers, %g0 ; however, the icc bits are modified as appropriate.

Using the "branch on not equal" instruction, we test the setting of the Z bit. If it is set to 1, the values were equal; the value in memory was a 6. If the Z bit is clear, the values were not equal and we jump to location main+0x5c .

While doing the branch, the delay instruction, nop , gets executed.

If the branch is not taken, we still execute the nop instruction and then continue to the following load instruction at location main+0x44 .

The branch on integer condition codes instructions do not generate traps.

Branch on FPU condition codes instructions

The fcc field of the floating-point status register, %fsr , is updated by the floating-point compare instructions. The branch on floating-point condition codes instructions test the fcc field and branches accordingly . As a reminder, here are the fcc codes.

fcc bits	Code	Relationship Between Two Floating Point Values
00	E	freg 1 = freg 2	Values were equal
01	L	freg 1 < freg 2	freg 1 less than freg 2
10	G	freg 1 > freg 2	freg 1 greater than freg 2
11	U	freg 1 ? freg 2	freg 1 and freg 2 are unordered

If a floating-point unit exists, the following branch instructions can be executed:

Table B-13. Branch instructions, FPU

Instruction Syntax	Operation	fcc Test
fba{,a} label	Branch always to label
fbn{,a} label	Branch never to label
fbu{,a} label	Branch on unordered	U
fbg{,a} label	Branch on greater	G
fbug{,a} label	Branch on unordered or greater	G or U
fbl{,a} label	Branch on less	L
fbul{,a} label	Branch on unordered or less	L or U
fblg{,a} label	Branch on less or greater	L or G
fbne{,a} label	Branch on not equal	L or G or U
fbe{,a} label	Branch on equal	E
fbue{,a} label	Branch on unordered or equal	E or U
fbge{,a} label	Branch on greater or equal	E or G
fbuge{,a} label	Branch on unordered, greater, or equal (not less)	E or G or U
fble{,a} label	Branch on less or equal	E or L
fbule{,a} label	Branch on unordered, less, or equal (not greater)	E or L or U
fbo{,a} label	Branch on ordered	E or L or G

These commands can generate fp disabled and fp exception traps, neither of which should cause panics. When one of these traps does occur, the operating system, not the hardware, is responsible for performing the floating-point operation.

Branch on coprocessor condition codes instructions

When this book was being written, there were no SPARC processor implementations that had yet incorporated a coprocessor. Even so, The SPARC Architecture Manual, Version 8 does define recommended instructions specific to the coprocessor.

The branch on coprocessor condition codes instructions assume there are two bits in the coprocessor status register that are used to represent conditions. The possible values for these two bits are: 0, 1, 2, and 3.

Here are the branch on coprocessor condition codes instructions.

Table B-14. Branch on coprocessor condition codes

Instruction Syntax	Operation Based on ccc
cba{,a} label	Branch always to label
cbn{,a} label	Branch never to label
cb3{,a} label	Branch on 3
cb2{,a} label	Branch on 2
cb23{,a} label	Branch on 2 or 3
cb1{,a} label	Branch on 1
cb13{,a} label	Branch on 1 or 3
cb12{,a} label	Branch on 1 or 2
cb123{,a} label	Branch on 1 or 2 or 3
cb0{,a} label	Branch on 0
cb03{,a} label	Branch on 0 or 3
cb02{,a} label	Branch on 0 or 2
cb023{,a} label	Branch on 0 or 2 or 3
cb01{,a} label	Branch on 0 or 1
cb013{,a} label	Branch on 0 or 1 or 3
cb012{,a} label	Branch on 0 or 1 or 2

Like the floating-point unit branch instructions, these instructions can cause coprocessor disabled and coprocessor exception traps. Both of these traps should not cause system panics and should instead cause the operating system to intervene and perform the required task.

The annul bit

The delayed transfer control instructions that we've seen all have an optional annul flag or bit which can be specified in the instruction by appending ,a to the instruction opcode. When set, the annul bit says to execute the delay instruction only if we take the branch. If we don't take the branch, a set annul bit annuls or nullifies the execution of the delay instruction; the delay instruction is not executed.

Here is the same snippet of assembly code we used earlier to demonstrate how a branch instruction might be used. This time, the bne instruction has been changed to bne,a.

 main+0x34:      ld      [%l4 - 0x8], %l0  main+0x38:      subcc   %l0, 0x6, %g0  main+0x3c:      bne, a  main + 0x5c  main+0x40:      nop  main+0x44:      ld      [%fp - 0x8], %l0 

This time, if the value in %l0 is not equal to 6, we will jump to main+0x5c while executing the nop instruction. Conversely, if the value in %l0 is equal to 6, we will skip the delay instruction all together and move on to the load instruction. Usually the delay instruction consists of something that does real work, instead of a nop . Unoptimized compiler output will often contain nop instructions.

For the "branch always" and "branch never" instructions, the delay instruction is executed if the annul bit is not set, and it is not executed when the annul bit is set.

Unconditional branches

Two instructions perform unconditional branches. They are:

Table B-15. Unconditional branch instructions

Instruction Syntax	Operation
call label	Save PC in %o7 and branch to label
jmpl address, reg	Save PC in reg and branch to address

The call instruction transfers control to an address relative to the current PC , whereas the jump and link, jmpl , instruction performs a register-indirect control transfer.

The call instruction places the current value of the Program Counter into register %o7 , whereas the jmpl instruction allows the programmer to specify in which register to store the PC .

The call instruction does not generate any traps.

The jmpl instruction generates a "memory address not aligned" trap when address is not word aligned.

Trap on integer condition codes instructions

We talk about traps in detail in another chapter. For now, let's just say that normally a trap is any condition in the hardware that shouldn't have occurred. Generalizing, we could say when an instruction is executing, if something goes wrong, the instruction gets stuck or trapped and can't finish its job. When this happens, the hardware suddenly switches to "Plan B," records the current Program Counter and jumps to a special trap handler. The operating system gets involved and may decide to panic, kill the offending program, or simply provide assistance to the hardware via software routines.

The SPARC processor offers the programmer a way to force a trap condition. Using the PSR icc field, a routine can test the condition codes and based on the results, force a trap. When the trap is "taken," the hardware still switches to "Plan B," records the PC , and jumps into the trap handler, specifically to the section set aside for software trap number specified as sw_trap_num . This is the way a user program actually issues a system call ” by trapping into the kernel with a specific code.

Here are the trap on integer condition codes instructions. You'll see that they are quite similar to the branch on icc instructions.

Table B-16. Trap on integer condition codes instructions

Instruction Syntax	Operation	icc Test
ta sw_trap_num	Trap always
tn sw_trap_num	Trap never
tne sw_trap_num (aka tnz)	Trap on not equal	not Z
te sw_trap_num (aka tnz)	Trap on equal	Z
tg sw_trap_num	Trap on greater	not (Z or (N xor V))
tle sw_trap_num	Trap on less or equal	Z or (N xor V)
tge sw _ trap_num	Trap on greater or equal	not (N xor V)
tl sw_trap_num	Trap on less	N xor V
tgu sw_trap_num	Trap on greater unsigned	not (C or Z)
tleu sw_trap_num	Trap on less or equal unsigned	C or Z
tcc sw_trap_num (aka tgeu)	Trap on carry 0 (> or = unsigned)	not C
tcs sw_trap_num (aka tlu)	Trap on carry 1 (<unsigned)	C
tpos sw_trap_num	Trap on positive	not N
tneg sw_trap_num	Trap on negative	N
tvc sw_trap_num	Trap on overflow clear	not V
tvs sw_trap_num	Trap on overflow set	V

The trap on integer condition codes instructions never execute the delay instruction.

These instructions all generate a trap instruction trap.

Orderly return from a trap

After a trap condition is handled by the operating system and everyone is happy again, instruction execution returns to the previously scheduled program that had caused the condition. The instruction, rett or return from a trap, does this control transfer.

Instruction Syntax	Operation
rett address	Return from trap, returning to address

Under various conditions, rett can cause any of the following traps.

Table B-17. rett traps

Trap Condition	How The Condition Is Caused
Illegal instruction	The bit-by-bit operation code of the instruction being executed did not represent a valid instruction.
Privileged instruction	The processor is not in privileged mode and the instruction being executed is a privileged instruction. Alternate address space instructions, stdfq and stdcq are all privileged instructions and will cause this condition when PSR bit S is 0.
Memory address not aligned	A double word, full word or half-word instruction is trying to access memory that is not double-word-, full-word- or half-word-aligned. Byte instructions can not cause this condition.
Window underflow	Register window management needed.

rett is a privileged instruction.