root@hpeos003[] cat infocache64.c #include <fcntl.h> #include <nlist.h> #include <time.h> #include <machine/cpu.h> #include <machine/pdc_rqsts.h> struct nlist64 stuff[] = { {"cache_tlb_parms"}, {"cpu_has_hw_tlb_assist"}, {0} }; main(argc, argv) int argc; char **argv; { int hwtlb; int unified_cache,unified_tlb; char *kernel; int incore; int pagesize; struct pdc_cache_rtn_block cache_tlb_parms; if ( argc != 2 ) kernel="/stand/vmunix"; else kernel=argv[1]; printf("Kernel = %s\n", kernel); if ( (nlist64(kernel, stuff)) < 0) { perror("nlist"); exit(1); } if ( (incore = open("/dev/mem", O_RDONLY)) < 0) { perror("incore"); exit(2); } if (lseek(incore, stuff[1].n_value, 0) < 0) { perror("lseek"); exit(3); } if (read(incore, &hwtlb, sizeof(hwtlb)) < 0) { perror("read"); exit(4); } if (lseek(incore, stuff[0].n_value, 0) < 0) { perror("lseek"); exit(4); } if ( (read(incore, &cache_tlb_parms, sizeof(struct pdc_cache_rtn_block)) ) < 0) { perror("read"); exit(5); } unified_cache = cache_tlb_parms.ic_conf.f_sel; unified_tlb = cache_tlb_parms.it_conf.p_sel; pagesize=(cache_tlb_parms.it_conf.page_size?4096:2048); printf( "\n" ); printf("HW page size is %d bytes\n", pagesize); printf("%sHW TLB walker%s\n",hwtlb?"":"NO ",hwtlb?" present":"" ); printf("TLB is %s\n",unified_tlb?"unified":"separate"); if ( unified_tlb ) printf("TLB size is %d entries\n", cache_tlb_parms.it_size); else { printf("I TLB size is %d entries\n", cache_tlb_parms.it_size); printf("D TLB size is %d entries\n", cache_tlb_parms.dt_size); } printf("\nCache is %s\n",unified_cache?"unified":"separate"); if ( unified_cache ) printf("cache size is %d bytes (room for %d pages)\n", cache_tlb_parms.ic_size,cache_tlb_parms.ic_size/ pagesize); else { printf("I cache size is %d bytes (room for %d pages)\n", cache_tlb_parms.ic_size,cache_tlb_parms.ic_size/ pagesize); printf("D cache size is %d bytes (room for %d pages)\n", cache_tlb_parms.dc_size,cache_tlb_parms.dc_size/ pagesize); } printf("\nOne cache line is %d bytes\n", cache_tlb_parms.ic_conf.blocksize*16); printf("Cache lines per chunk: %d\n", cache_tlb_parms.ic_conf.lines_per_chunk ); } root@hpeos003[] root@hpeos003[] getconf KERNEL_BITS 64 root@hpeos003[] echo "cpu_arch_is_2_0/D" adb /stand/vmunix /dev/kmem cpu_arch_is_2_0: cpu_arch_is_2_0: 1 root@hpeos003[] cc +DD64 -lelf -o infocache64 infocache64.c root@hpeos003[] ./infocache64 Kernel = /stand/vmunix HW page size is 4096 bytes NO HW TLB walker TLB is unified TLB size is 240 entries Cache is separate I cache size is 786432 bytes (room for 192 pages) D cache size is 1572864 bytes (room for 384 pages) One cache line is 64 bytes Cache lines per chunk: 1 root@hpeos003[] |