Eight-chip Complementary Code Keying (CCK) is used as the modulation method for HRDSS (5.5 and 11 Mbps) transmissions. The CCK chip signaling rate is 11 MHz and is the same as that of DSSS. The signal bandwidth of CCK is therefore also 11 MHz and is compatible with DSSS systems. The HRDSSS basic packet format is the same as that of DSSS. An optional short packet format is also provided to reduce transmission overhead for 2-, 5.5-, and 11-Mbps rates. An optional HRDSSS packet binary convolutional coding (PBCC) modulation method can also be used in place of the CCK modulation. 10.4.1 Summary of 802.11b StandardsTwo different preambles and headers are defined: the mandatory supported long preamble and header, which is interoperable with the 1- and 2-Mbps DSSS specification, and an optional short preamble and header. Figure 10.26 shows the long packet format for HRDSSS transceivers. The long packet format is the same as that used by DSSS transceivers. There are several new definitions in the Signal and Service fields. High rates and corresponding encodings are different in the Signal field. A bit is used in the Service field to indicate the length that is expressed in whole microseconds. Another bit is used in the Service field to indicate whether the optional PBCC mode is being used. One bit is used in the Service field to indicate that the transmit carrier frequency and bit clocks are locked. Figure 10.26. Long Packet FormatFigure 10.27 shows the optional short packet format for HRDSSS transceivers. The short packet format also consists of a preamble, a header, and a MAC frame. The short packet format preamble has a Sync field of only 56 scrambled 0 bits and a Start Frame Delimiter of 16 bits. The short packet format SFD is the time reversal of long packet format SFD. The short packet format SFD has a binary pattern of 0000 0101 1100 1111 transmitted lsb first. The short packet format header also has a Signal field of 8 bits, a Service field of 8 bits, a Length field of 16 bits, and a CRC field of 16 bits. The CRC is generated using the same CCITT CRC-16 polynomial of G(x) = x16 + x12 + x5 + 1. The short packet format preamble uses the 1-Mbps Barker code DBPSK modulation. The short packet format header uses the 2-Mbps Barker code DQPSK modulation, and the MAC frame is transmitted at 2, 5.5, or 11 Mbps. All bits in an HRDSSS packet are scrambled with the same self-synchronizing scrambler based on the generator polynomial of G(z) = z 7 + z 4 + 1. Figure 10.27. Short Packet FormatThe CCK modulation for HRDSSS wireless Ethernet was jointly proposed by Harris and Lucent during the 1998 July 802.11b working group meeting. Before that joint proposal, both companies made similar but different modulation proposals based on the 11-MHz chip signaling rate for HRDSSS. Lucent proposed the Barker code pulse position modulation (BCPM) method and Harris proposed the M-array Bi-Orthogonal Keying (MBOK) and Quadrature M-array Bi-Orthogonal Keying (QMBOK) methods. The joint CCK proposal uses 4 bits to select an eight-chip code word among 16 code words for 5.5 Mbps and 8 bits to select an 8-chip code word among 256 code words for 11 Mbps. Because each chip can be represented by a binary complex number for the in-phase and the quadrature channels, significant distances are maintained among different code words. Lucent's earlier BCPM [2] proposal defined eight different pulse positions for the Barker code chip sequence (i.e., the original Barker code and seven additional time-rotated versions are used for signaling). Three additional bits can be carried on each symbol if in-phase and quadrature channels use the same time-rotated Barker code, and six additional bits can be carried on each symbol if in-phase and quadrature channels can choose their time-rotated Barker codes independently. These additional 3 and 6 bits lead to transmission rates of 5 and 8 Mbps, respectively. The transmission rate can be further increased to 8 x 11/9 = 9.78 if the symbol duration is reduced to 9 chips instead of 11. To recover bit information carried in pulse positions, channel equalization techniques are necessary to minimize the effect of intersymbol interference caused by channel dispersion. Harris's MBOK and QMBOK proposal is based on modified Walsh codewords. Walsh codewords have the property of high autocorrelation and zero cross correlation or orthogonality. Walsh codewords are rows of Hadamard matrix Hi, where i is the matrix dimension. A Hadamard matrix of dimension 2n can be constructed based on a Hadamard matrix of dimension n. We have Equation 10.11 where is the sign reversal version of Hn. Starting with H1=[1], we have Harris's modified Walsh codewords can be described by rows of the following matrix. All columns of this modified Walsh code matrix Hm8 can be identified by a codeword or its sign reversal of.H8. Equation 10.12 MBOK uses 3 bits to select one codeword from the preceding eight codewords and 1 bit to reverse signs of every bit in the codeword. The transmission rate of MBOK is therefore 4 x 11/8 = 5.5 Mbps. QMBOK uses 4 bits for the in-phase channel codeword and another 4 bits for the quadrature channel codeword independent selections. The transmission rate of QMBOK is 8 x 11/8 = 11 Mbps. These modified Walsh codewords are called bi-orthogonal for zero cross correlation between codewords except for codeword pairs with reversed signs where the cross correlation is the negative of the autocorrelation. Polyphase complementary codes were eventually adapted by the 802.11b standards for their better performance at 11 Mbps especially in the multipath environment with cross in-phase and quadrature channel interference [3]. Unique features of a pair of binary complementary codewords were first discovered by Marcel J. E. Golay in 1951 [4] and further discussed in 1961 [5]. Golay used a pair of binary sequences as shown in Figures 10.28 and 10.29 to demonstrate these features. Figure 10.28. Example Complementary Binary Sequence 1Figure 10.29. Example Complementary Binary Sequence 2Sequence 1 has four pairs of like elements and three pairs of unlike elements, both with a separation of one; whereas Sequence 2 has four pairs of unlike elements with a separation of one and three pairs of like elements. Complementary codes are defined as a pair of equal finite-length sequences having the property that the number of pairs of like elements with any given separation in one series is equal to the number of pairs of unlike elements with the same separation in the other. Complementary codes are characterized by the property that their aperiodic autocorrelation is zero everywhere except at the zero shift. Let the ith complement codeword of n elements be and the aperiodic autocorrelation of the code word be . For a pair of complementary codewords, we have Equation 10.13 The concept of a complementary codeword pair was late extended to a set of N complementary codewords [6]. Similarly, we have Equation 10.14 Elements of complementary codewords were further extended to have multiple phases of unit magnitude instead of only binary values (i.e., , I = 0, 1, 2, …, L 1, q = 2p/L instead of ). The aperiodic autocorrelation of polyphase complementary codewords becomes where is a complex conjugate of and Equation 10.14 still holds. Methods of finding polyphase complementary codewords of various lengths were also discovered [7, 8]. CCK length 8 polyphase complementary codewords can be obtained based on length 4 polyphase complementary codewords. Length 4 polyphase complementary codewords are derived by obtaining one pair of complementary codewords at a time. A pair of length 4 polyphase complementary codewords has the following general formats. We have a polyphase codeword, , and its complementary polyphase codeword, . A pair of length 4 polyphase codewords is defined by Equation 10.15 General formats for a pair of length 4 complementary polyphase codewords become and . f0and q0 can be considered as a rotation to either codeword, respectively. By setting f0 = 0, and q0 = 0 and observing ep = 1, we have and . For f1 = ¼/2, we have and . Rotating S4 and C4 by setting f0 = ¼/2, ¼, 3¼/2, and q0 = ¼/2, ¼, 3¼/2 independently, we obtain 16 pairs of, or 32, length 4 polyphase complement codewords. Next, pairs of length 8 polyphase complementary codewords are formed using pairs of length 4 polyphase complementary codewords. We have and . By setting f0 = 0, ¼/2, ¼, 3¼/2, we can form 64 pairs of, or 128, length 8 polyphase complementary codewords. Another 64 pairs of, or 128, length 8 polyphase complementary codewords can be formed using and . These polyphase complementary codewords are described by the IEEE 802.11b standards as Equation 10.16 where 1,2,3, are defined by data bits D =d0d1d2d3d4d5d6d7. Specifically, 1 is a rotation fact of the codeword and is determined by bit pairs d0d1. 00, 01, 11, and 10 bit pairs of d0d1 specify 0, p/2, p, and p/2 phase rotation of the codeword, respectively, for even symbols. Data bits d0d1 are complemented first for odd symbols. 2,3, and 4 are determined by bit pairs d2d3,d4d5 , and ,d6d7 respectively. 00, 01, 11, and 10 pairs of d2d3, d4d5, , and d6d7 specify 0, p/2, p, and p/2 phase for , 2, 3 and, 4 respectively. Assuming 0 value for 1, polyphase complementary codewords corresponding to bit values of d2d3d4d5d6d7 are listed in Table 10.2 where 0, p/2, p, and p/2 phases are represented by 0, 1, 2, and 3, respectively.
For 5.5-Mbps transmission, only four polyphase complementary codewords and their rotations are required. After extensive computer simulation studies, these four polyphase complementary codewords, listed in Table 10.3, are selected for their outstanding performance under various multipath wireless channel conditions. The first two bits are used again to rotate these codewords according to these same even and odd symbol rules.
These various multipath channel models used for simulation performance studies can be described by Equation 10.17 Equation 10.18 Equation 10.19 where is a zero mean Gaussian random variable with variance produced by generating an N(0,1) Gaussian random number and multiplying it by , and is chosen so that the condition is satisfied to ensure the same average received power. Ts represents the sampling period, and TRMS represents the delay spread of the channel. The number of samples to be taken in the impulse response should ensure sufficient decay of the impulse response tail (e.g., kmax = 10 x TRMS/TS). For a sampling rate of 11 MHz, we have TS = 1/fsample 91 ns. For TRMS = 200 ns, we have kmax = 10 x 200/90 23. Figure 10.30 shows a corresponding channel model. Figure 10.30. A Multipath Channel ModelBefore finalizing the adaptation of the CCK modulation for 802.11b, another binary convolution code (BCC) based modulation proposal was presented by Alantro, which later became a subsidiary of Texas Instruments, Inc. It was argued that BCC can provide additional coding gain for its Trellis structure and that the multipath channel effect can be minimized by using scrambling. Although not accepted as the standardized modulation method, texts for the Direct Sequence Spread Spectrum with packet binary convolution code (DSSS/PBCC) were included in the 802.11b standards as an optional modulation method. The binary convolution code proposed for DSSS/PBCC is defined by the Equation 10.20 or in octal form shown by Equation 10.21 The convolution encoding process can be implemented with six delay elements and exclusive OR operations as shown in Figure 10.31. For every data bit input x, two output bits y0 and y1 are generated. Figure 10.31. A DSSS/PBCC Encoder Implementation (From IEEE Std. 802.11. Copyright © 1999 IEEE. All rights reserved.)The output of the binary convolutional code is mapped to a constellation using one of two possible rates. The 5.5-Mbps rate uses BPSK, and the 11-Mbps rate uses QPSK. In BPSK mode, each pair of output bits from the encoder is taken serially (y0 first) and used to produce two consecutive BPSK symbols. In QPSK mode, each pair of output bits is used to produce one symbol. A 256-bit pseudo-random sequence is generated from a 16-bit seed sequence of 0011001110001011 for scrambling. This 256-bit sequence is produced by using the 16-bit seed sequence 16 times. More precisely, this 256-bit sequence is formed by using the original 16-bit seed sequence as the lead and is followed by 15 left-rotated versions of the seed sequences in steps of a 3-bit left-rotate for each subsequent sequence. This 256-bit sequence is used for scrambling by rotating the QPSK symbols by 90° and reversing the sign of x-axis for BPSK symbols when a 1 bit is encountered. The transmission throughput of a DSSS/PBCC system can be increased to 22 Mbps if the 8-phase shift keying (8PSK) modulation method is used. The transmit power level and the PSD mask of HRDSSS are the same as those defined for DSSS for spectrum compatibility where different HRDSSS and DSSS transceivers can share the same spectrum to operate. On the other hand, the minimum separation frequency is reduced to 25 MHz for non-overlapping channels. Three non-overlapping channels with carrier frequencies at 2.412, 2.437, and 2.462 GHz and six overlapping channels with carrier frequencies at 2.412, 2.422, 2.432, 2.442, 2.452, and 2.462 are defined for North American HRDSSS operations. 10.4.2 Transceiver Architecture and Performance EstimationFigure 10.32 shows a functional block diagram of a typical HRDSSS wireless Ethernet transceiver. Compared with that of a DSSS transceiver, the differences are the modulation part before DAC and the demodulation part after ADC. In the transmit path, instead of spreading with Barker code of 11 chips for 1 or 2 bits, a complementary codeword of 8 chips is selected for every 4 or 8 bits. In the receiving path, instead of despreading, a pair of matched filters are used. Higher sampling rate ADCs are necessary for the implementation of matched filters. Outputs from matched filters are decimated to the chip signaling rate and then correlated with 4 or 64 codewords using the fast Walsh transform algorithm to identify the correct symbol and its rotation angle. Identified symbols are then decoded into bit streams. Figure 10.32. HRDSSS Transceiver StructureA desired codeword can be created in a few steps. The first 2 bits of each group of 8 bits are reserved for codeword rotation. The next three pairs of bits are used to create three base phases, 1, 2, and 3. These three phases are then used to generate phases of the first seven chips; the last chip always has a 0 phase. A codeword is constructed based on phases of these eight chips resulting in a pair of real and imaginary eight-chip sequences with values of 1, 0, and +1. This pair of sequences might be swapped or sign-reversed depending on values of the first pair of 2 bits and the even/odd symbol rule. On the other hand, a lookup table can also be used to pick up a codeword among 64 with 6 input data bits; the codeword is then rotated based on the other 2 input data bits. The demodulator of a RAKE receiver (whose structure is similar to that of a garden rake) can be implemented with a combination of a pair of higher sampling rate matched filters for SNR optimization, a modified fast Walsh transform operation for codeword identification, and maybe a decision feedback channel equalizer for channel interference cancellation. The frequency response of a matched filter is the complex conjugate of the received signal. In other words, the time domain response of a matched filter is the same as that of the received signal. Filter coefficients of these matched filters can be identified by comparing received signal against the known preamble of Sync and SFD fields at the beginning of a packet under the high SNR condition. In a low SNR environment, the time domain response of a matched filter can be based on the accumulation effect of those known transmitter and receiver filters. Right-multiplying a Hadamard matrix (consisting of Walsh codewords) by an input data vector is defined as a Walsh transform as shown by Equation 10.22 where X is an input column vector of size N, HN is a Walsh-Hadamard matrix of dimension N by N, and Y is the output column vector of size N. The original data vector can be recovered by the inverse Walsh transform of the output column vector Y, as defined by Equation 10.23 A two-dimensional Walsh transform is also defined, as shown by Equation 10.24 where X, HN, and Y all are dimension N by N matrices. The inverse two-dimensional Walsh transform is shown by Equation 10.25 A Walsh transform of a data vector of size N takes N2 addition and/or subtraction operations. A fast Walsh transform (FWT) can be implemented to reduce the required number of operations to N log2 N. The FWT is derived based on the partition of a Hadamard matrix into a product of log2 N matrices whose rows only have two nonzero entries. Define a special matrix operator and the construction of a Hadamard matrix can also be described by the following Kronecker product operation [9]: Equation 10.26 For example, we have Equation 10.27 More interestingly, the construction of a Hadamard matrix can also be described by the following Kronecker product operation on 2 by 2 identity matrices [10]: Equation 10.28 where has only two nonzero entries on each row. For example, we have Equation 10.29 Similarly, we have Equation 10.30 For this example, these three matrix multiplications, starting from the rightmost, lead to the butterfly structure shown in Figure 10.33. Figure 10.33. Fast Walsh Transform Butterfly StructureThis FWT cannot be used for the quadrature phase complementary codewords directly. Similar fast transformations involving only one operation between a pair of numbers can be derived by examining relationships between pairs of adjacent bits, groups of four bits, and valid codewords. A butterfly structure for processing quadrature phase complementary codewords using the FWT principle is shown in Figure 10.34. From each data point, the top line indicates an addition, the second a 90° rotated addition, the third a subtraction, and the bottom a 90° rotated subtraction. Notice that chip 2 (X6), and chip 5 (X3) are negated before the execution of the butterfly computation. Only two of the three stages of operation are included in Figure 10.34. The last stage of the operation pairs an output from the second stage of the left block with one from the second stage of the right block of the same row and performs +, j, , and j calculations. Inputs X0 through X7 are either real or imaginary for an ideal channel and can be complex numbers owing to channel distortion. A real operation adds or subtracts real and imaginary components separately. An operation involving j adds or subtracts real components to or from imaginary ones and vice versa. There are 64 complex outputs from the last stage of the butterfly operation. The output with the largest amplitude indicates matched codewords. The phase of the output indicates the rotation of the codewords. Figure 10.34. Fast Walsh Transform to a Quadrature Input VectorThis modified FWT for quadrature phase complementary codewords can also be described by the following matrix expression involving 8 by 16, 16 by 32, and 32 by 64 matrices whose rows contain only two nonzero elements: Equation 10.31 where , and . The use of this modified FWT can reduce the required number of operations for codeword correlation from 8 x 64 = 512 to 16 + 32 + 64 = 112. MATLAB programs for the binary and modified Walsh transforms are included at the end of this chapter. A Decision Feedback Equalizer (DFE) can use identified symbols to cancel interchip interference as shown in Figure 10.35. Identified symbols from the FWT are decoded into data bits and also used to retrieve the write codeword of corresponding chips with real and imaginary components. The DFE with coefficients calculated from the estimated channel impulse response uses these chips to subtract interchip interference from matched filter outputs. Interchip interference cancellation is performed eight chips at a time in conjunction with the availability of each arriving symbol. On the other hand, the cancellation value for each chip needs to be accumulated across symbol boundaries. Figure 10.35. Application of a Decision Feedback EqualizerFigure 10.36 shows an example of a HRDSSS transceiver chip set from Intersil. This chip set consists of a MAC part, a baseband processor, an IF modem, an RF/IF convertor, and a power amplifier. Figure 10.36. HRDSSS Transceiver Chip Set ExampleDetails of the baseband transmit block are shown in Figure 10.37. Data bits are first passed through the scrambler. A preamble and a header are attached before the Barker code or CCK modulation for 1, 2 or 5.5, 11 Mbps, respectively. Data symbols are then passed through transmit filters before reaching DACs. An AGC is used to regulate the transmit power. The gain and the output power level of a Power Amplifier might vary considerably because of different variations introduced during the manufacturing process. If not regulated, the transmit power level might vary in a range of 5 dB. That might lead some transceivers to exceed the power limits and others to not transmit enough power. The power level of the PA is monitored through an ADC and the gain of the IF amplifier is properly controlled through a DAC via an AGC loop. Figure 10.37. Baseband Transmitter StructureDetails of the baseband receiver block are shown in Figure 10.38. Received signals from DACs are first interpolated for timing adjustment. Digitized samples with correct timing are selected by the down converter and passed through matched filters. A Barker code correlator or an FWT-based CCK correlator is used for symbol identification for 1/2 Mbps (or 5.5/11 Mbps) throughputs. A DFE and a more accurate timing/carrier recovery PLL are used for the HRDSSS operation. In the receiver path, the gain is adjusted in two stages. The gain of the RF amplifier is controlled by a DAC according to the dynamic range of the digitized signal while a fixed gain in the IF stage can be turned on and off depending on the signal level detected by the CCA functional block. Some coordinations are required between RF and IF gain adjustments. Figure 10.38. Baseband Receiver StructureThe transmit power of an HRDSSS transceiver is also defined to be below 30 dBm. An HRDSSS transceiver needs to operate under the received signal level of 10 dBm when transceivers are close by. The receive sensitivity is required to be 76 dBm for the 11-Mbps CCK modulation. The allowed signal attenuation is between 76 and 106 dB for a transmit power of 0 and 30 dBm, respectively. The maximum operable distance between transceivers could exceed 1000 ft at the 30-dBm transmit power level in a barrierless and low noise transmission environment. The receiver front-end noise level is the same as that of DSSS because it is in the same signal bandwidth and is equal to 89.59 dBm. At a signal-to-noise level of about 13.59 dB, the channel capacity for the DSSS environment is Equation 10.32 The transmission performance of an HRDSSS wireless Ethernet transceiver can be further studied by computer simulation. Figure 10.39 shows a simplified Simulink model which consists of a random data sequence generator, a transmitter, a multipath channel model, and a receiver. Figure 10.39. A Simulink HRDSSS Simulation ModelFigure 10.40 shows the internal structure of the Simulink transmitter model. A binary data sequence is fed through the CCK encoder to generate in-phase and quadrature chips at a chip rate of 11 megahertz per second (MHz/s). The sampling rate of these chips is further increased tenfold for low-pass filtering. These two fourth-order Butterworth low-pass filters have corner frequencies at 5.5 MHz. To use the baseband multipath channel model, the modulation process is omitted. Figure 10.40. The Simulink HRDSSS Transmitter ModelFigure 10.41 shows a possible implementation of the CCK encoder. Four pairs of bits are formed to generate four individual base phases after the serial-to-parallel conversion. Eight phases are then calculated for each individual chip. These phases are then translated to in-phase and quadrature chip values via separate parallel-to-serial conversion processes. Figure 10.41. A Simulink CCK Encoder ModelFigures 10.42 and 10.43 show bit-to-phase conversion circuits for the first phase, corresponding to the first and the second bits, and for the rest of the phases. Figure 10.42. Bit-to-Phase Encoder IFigure 10.43. Bit-to-Phase Encoder IIFigure 10.44 shows the multipath channel model consisting of in-phase and quadrature FIR filters whose coefficients are calculated according to Equations 10.17, 10.18, and 10.19. Figure 10.44. A Simulink Multipath Channel ModelFigure 10.45 shows the internal structure of the Simulink receiver model. With the demodulation process omitted for simplicity, received signals are passed through the in-phase and the quadrature-matched filters first. Filtered signals are then decimated to the original chip rate of 11 MHz. An FWT is used to generate 64 codeword correlation outputs. These correlation outputs are converted to four base phases by the four-phase decoder. Original bit streams are recovered by the phase-to-bit (P2B) decoder. Original chips are also recreated by the phase-to-chip (P2C) decoder to be used by the decision feedback channel equalizer for interchip interference cancellation. Figure 10.45. The Simulink HRDSSS Receiver ModelFigure 10.46 shows the implementation of the FWT functional block, which consists mainly of three matrices, each of which has only two nonzero entries in each row, as described by Equation 10.31. Figure 10.46. A Simulink FWT ModelFigure 10.47 shows a possible implementation of the four-phase decoder. One of these 64 correlation outputs is selected for its maximum magnitude. Four base phases are then produced corresponding to that selection and the phase angle of that selected autocorrelation output. Figure 10.47. A Simulink Codeword Decoder ModelFigure 10.48 shows the implementation of one of these 64 four-phase generation cells. After a cell is activated by matching the maximum input InM and the corresponding input InA, a phase angle related to the corresponding input as well as three other stored phases are made available to the output. Figure 10.48. A Phase Identification CellFigure 10.49 shows the implementation of the phase-to-bit decoder. It consists of four individual phase-to-bit conversion cells, corresponding to 4 bit pairs, and a parallel-to-serial convertor. Figure 10.49. A Simulink Phase-to-Bit DecoderFigures 10.50 and 10.51 show implementations of phase-to-bit conversion cells corresponding to the first pair and to the remaining three pairs of bits because of the different bit-to-phase encoding rules. Figure 10.50. Phase-to-Bit Decoder IFigure 10.51. Phase-to-Bit Decoder IIFigure 10.52 shows the implementation of the phase-to-chip sequence decoder. These four base phases are used to formulate the phases of eight individual chips. Formulated individual phases are then converted to values of +1, 0, and 1 for in-phase and quadrature parts of a chip sequence with the help of two separate parallel-to-serial convertors. Figure 10.52. A Phase-to-Chip Decoder |