8.2 1394-1995 Cable Physical Layer Attributes

The 1394 shielded twisted pair cable-based physical layer can be characterized by its packet format, transceiver circuit, DATA/STROBE line code, and PSDs.

8.2.1 Packet Formats

There are three types of packets exchanged between FireWire transceivers. There are physical layer packets used during initialization and link management, primary packets for carrying asynchronous and isochronous data, and an acknowledge packet for reception of asynchronous packet acknowledgment. The general format of the physical layer packet is shown in Figure 8.15. The first 4 bytes of a physical layer packet consists of a packet type of 2 bits, a physical_ID of 6 bits, and a body of 3 bytes. The last 4 bytes of a physical layer packet are the logic inverse of the first 4 bytes for error detection parity checking. A physical layer packet is ignored if the logic inverse of the last 4 bytes does not match the bit pattern of the first 4 bytes.

Figure 8.15. Physical Layer Short Packets

There are three subtypes of physical layer packets: self-ID (xx = 10), link-ON (xx = 01), and PHY configuration (xx = 00). The body of the first self-ID packet contains information on link active indication, gap_cnt, transmission throughput capabilities, a delay parameter, link management capability, power supply capabilities, and port status. Gap_cnt is a value used for calculating subaction and reset gap timing. Up to three additional self-ID packets can be delivered if a node has more than 3 ports to reveal the status of up to 27 ports. The body of a link-ON packet consists of 3 zero-bytes. The body of a PHY management packet has 1 byte consisting of an R bit, T bit, and 6-bit gap_cnt followed by 2 zero-bytes. The R bit is used to set up a root, and the T bit is used to set up the gap_cnt.

A primary packet can be either an asynchronous or isochronous packet. An asynchronous packet consists of a header of 12 or 16 bytes followed by a 4-byte header CRC and a data field of a multiple of 4 bytes in length followed by a 4-byte data CRC as shown in Figure 8.16.

Figure 8.16. Asynchronous Packet

The header of an asynchronous packet consists of a 2-byte destination_ID, a 6-bit transaction label, a 2-bit retry code, a 4-bit transaction code, a 4-bit priority code, a 2-byte source_ID, and 6 or 10 bytes of packet-type-specific information as shown in Figure 8.17. There are 10 subtypes of asynchronous packets for read and write requests and responses with or without the data field as well as for cycle start. An acknowledge packet has only 1 byte including 4 code bits and 4 parity bits, which are the logical inverse of the preceding code bits as shown in Figure 8.18.

Figure 8.17. Header of an Asynchronous Packet

Figure 8.18. Acknowledge Packet

An isochronous packet consists of a 4-byte header followed by a 4-byte header CRC and a data field of a multiple of 4 bytes in length followed by a 4-byte data CRC as shown in Figure 8.19. The header of an isochronous packet consists of a 2-byte data length, a 2-bit data format tag, a 6-bit channel number, a 4-bit transaction code, and a 4-bit synchronization code as shown in Figure 8.20.

Figure 8.19. Isochronous Packet

Figure 8.20. Header of an Isochronous Packet

CRC for header and data of both asynchronous and isochronous packets is implemented using the same generator polynomial as that used by the Ethernet:

Equation 8.4

The same CRC generation and checking procedures are also adapted. The CRC values are generated with the following procedures.

1. The first 32 bits of the header or data field are complemented to avoid initial zeros normally found in the destination ID.

2. The n bits of the field are considered to be the coefficients of a polynomial of degree n 1.

3. The degree of the field polynomial is raised to n + 31 by multiplying the original by x³².

4. The field polynomial is then divided by G(x) to produce a remainder of degree < 32.

5. The remainder sequence of 32 bits is complemented to become CRC.

8.2.2 Transceiver Circuits

Figure 8.21 shows typical implementations of a FireWire transceiver. For each twisted pair, a differential driver and a differential receiver are used for strobe and data signaling and reception. In addition, threshold detectors with positive and negative bias are used specifically to recognize arbitration level pullings. A speed indication common mode bias is also applied to twisted pair B via high-impedance current sources. That common mode bias is feedback to a circuit also attached to twisted pair B for Port_Status monitoring. That same common mode bias is detected by a transceiver at the other end of the twisted pair (twisted pair A) to decide which transmission throughput should be agreed upon.

Figure 8.21. FireWire Transceiver Circuits (From IEEE Std. 1394-1995. Copyright © 1995 IEEE. All rights reserved.)

There are three recognizable twisted pair arbitration statuses: 0, 1, and Z corresponding to the activation of the negatively biased threshold detector, to the activation of the positively biased detector, and to no activation of both detectors. Examining both twisted pairs for three possible statuses results in nine different arbitration signals that can be detected. They can be derived by combining six different signals originated from both ends of two twisted pairs. For example, Z and Z represent idle, 1 and 1 represent bus reset, Z on twisted pair A and 0 on twisted pair B represent a request to transmit from a child to a parent and a grant to transmit from a parent to a child, a 0 on twisted pair A and a 1 on twisted B represent a data prefix, etc. The arbitration status of 1 is declared when the differential voltage is larger than 168 mV, 0 is declared when the voltage is less than 168 mV, and Z is declared when the voltage is between 89 and 89 mV.

The data sequence is transmitted using binary nonreturn to zero (NRZ) pulses. Instead of using the conventional data and clock signaling, the data sequence is sent via twisted pair B and a strobe sequence is sent via twisted pair A. The strobe sequence changes from 0 to 1 and vice versa whenever two consecutive data bits are the same as shown in Figure 8.22. This encoding mechanism ensures that transitions occur every bit interval among both pairs. At the receiver side, the clock can be recovered by the exclusive OR operation of data and strobe sequences. The amplitude of data and strobe signaling voltage is in the range of 172 to 265 mV for 1 and 172 to 265 mV for 0.

Figure 8.22. Data-Strobe Encoding (From IEEE Std. 1394-1995. Copyright © 1995 IEEE. All rights reserved.)

Transmission throughputs of 98.304, 196.608, and 393.216 Mbps are defined by the 1394-1995 standards document as S100, S200, and S400 data rates. They are indicated by common mode bias voltage of 1.665, 1.438, and 1.03 V, respectively.

Power spectrum densities for FireWire of different throughputs can be calculated according to

Equation 8.5

where T is the period of a bit. PSDs for S100, S200, and S400 are shown in Figure 8.23 with u = 0.2 V and R = 110 ohms.

Figure 8.23. FireWire Power Spectrum Densities