The System's Virtual Address Space The VAS is an organizational concept that allows the implementation of shared and private memory objects through a single level of address abstraction. This approach is part of the PA-RISC processor design and is supported in the HP-UX kernel code as part of its hardware-dependent layer. As we learned in our discussion of PA-RISC computing platforms, the VAS is conceptually arranged as a large grid, and each column represents a unique virtual space containing four quadrants (represented by four rows). In Figure 6-2, we see the practical application of this VAS model. As a process uses its vas and pregions to map various memory objects to specific offsets within its logical memory view, these objects are mapped to corresponding regions of virtual pages in the system VAS. Physical pages are in turn mapped to specific virtual pages by hardware functionality (pdir and tlb) supported by kernel fault handlers and resource managers. Figure 6-2. Populating the VAS with Regions 
During execution, the PA-RISC hardware utilizes the translation lookaside buffer (tlb) and the page directory (pdir) to convert implicit virtual addresses to physical addresses. When a requested virtual address is not resident, or in-core, the hardware suffers a page fault. It is at this point that the kernel fault-handling code must come into play, find (or create) the missing page image, load it in an available physical page frame, update associated hardware-dependent layer data structures, update kernel hardware-independent layer data structures, and then return from the fault handler so that the hardware may request the address again. The kernel must keep track of which regions occupy which quadrants in which space. This is accomplished by a host of bit maps and resource maps maintained by the kernel. A key feature of this approach has been that even though the scope of virtual addressing increased many orders of magnitude when the underlying hardware grew from 32 bit to a 64 bit, the VAS concept has changed very little. True, the quadrants are much larger and there are many more potential spaces, but the concept remains consistent. The core issue for both the processor hardware and the kernel is the translation of virtual-to-physical translation and, to a lesser degree, physical-to-virtual mapping. |
