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Digital systems that implement multiplication
A half or full adder will be found at the center of all arithmetic circuits. The full adder can be constructed from cascaded half adders. Multibit adders are constructed from cascaded full adders. Since the performance of such adders is limited by the serial "rippling" of the carry from one adder stage to the next, designers have developed parallel carry look-ahead circuits for fast adders. This is a very good example of the trade-off between hardware and speed. The ripple adder is much slower than the look-ahead adder, but the latter achieves its high speed at the expense of many more gates.
Adders for binary-coded decimal numbers are built from cascaded full adders. They look much like conventional binary adders, with extra circuitry to correct the sum of two BCD digits when it exceeds nine. A 4-bit BCD adder needs six full adders.
Multipliers are also formed by combining cascaded full and half adders. We saw how to construct a 4-by-4 bit multiplier using 12 full adders. We also looked at ways to use the 4-by-4 multiplier as a fundamental building block, in conjunction with even more adders, to build multipliers of larger bit widths. The 8-by-8 multiplier we designed used a considerable amount of logic, but much less than if we had built the multiplier directly rather than using 4-by-4 multiplier building blocks.
The arithmetic logic unit, or ALU, is an ubiquitous circuit component that implements both logic and arithmetic operations over data inputs. ALUs can be found embedded in just about every digital system that manipulates numbers. Any of the design strategies covered in Chapters 2 through 4 can be used to implement ALUs, including two-level, multilevel, and even ROM-based approaches.
Computer arithmetic is a complex topic worthy of its own advanced course. There are several comprehensive textbooks on the underlying mathematics of number systems and the hardware to implement arithmetic operations over them. K. Hwang's Computer Arithmetic, Wiley, New York, 1979 is one of the best known.
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This file last updated on 07/14/96 at 05:41:25.
Chapter Review
In this chapter, we have examined the basic representations of numbers within digital systems and the primitive circuits for their arithmetic manipulation. In all digital systems, positive integers are represented in the same way. The difference is in how negative numbers and zero are represented. The primary representation schemes are(1) sign and magnitude, (2) ones complement, and (3) twos complement. Twos complement is the most pervasively used representation, because of the single representation for zero and the ease with which a binary adder can be used to implement both addition and subtraction operations. The latter is accomplished simply by adding the twos complement of the number to be subtracted.Digital systems that implement multiplication
(and division) hardware also need to support the sign and magnitude representation. All of the circuits we have shown for multiplication are based on number magnitudes. This means that a system that uses twos complement for addition/subtraction and sign and magnitude for multiplication and division must provide additional circuitry to convert between the forms and handle the sign correctly.A half or full adder will be found at the center of all arithmetic circuits. The full adder can be constructed from cascaded half adders. Multibit adders are constructed from cascaded full adders. Since the performance of such adders is limited by the serial "rippling" of the carry from one adder stage to the next, designers have developed parallel carry look-ahead circuits for fast adders. This is a very good example of the trade-off between hardware and speed. The ripple adder is much slower than the look-ahead adder, but the latter achieves its high speed at the expense of many more gates.
Adders for binary-coded decimal numbers are built from cascaded full adders. They look much like conventional binary adders, with extra circuitry to correct the sum of two BCD digits when it exceeds nine. A 4-bit BCD adder needs six full adders.
Multipliers are also formed by combining cascaded full and half adders. We saw how to construct a 4-by-4 bit multiplier using 12 full adders. We also looked at ways to use the 4-by-4 multiplier as a fundamental building block, in conjunction with even more adders, to build multipliers of larger bit widths. The 8-by-8 multiplier we designed used a considerable amount of logic, but much less than if we had built the multiplier directly rather than using 4-by-4 multiplier building blocks.
The arithmetic logic unit, or ALU, is an ubiquitous circuit component that implements both logic and arithmetic operations over data inputs. ALUs can be found embedded in just about every digital system that manipulates numbers. Any of the design strategies covered in Chapters 2 through 4 can be used to implement ALUs, including two-level, multilevel, and even ROM-based approaches.
Further Reading
Elements of this chapter were drawn from several previous logic design textbooks, primarily C. H. Roth's Fundamentals of Logic Design, West, St. Paul, 1985, and Johnson and Karim's Digital Design: A Pragmatic Approach, PWS, Boston, 1987. The 8-by-8 bit multiplier case study is based on the application note associated with the 74284/285 data sheet in the Texas Instruments' TTL Data Book, Volume 2, 1985.Computer arithmetic is a complex topic worthy of its own advanced course. There are several comprehensive textbooks on the underlying mathematics of number systems and the hardware to implement arithmetic operations over them. K. Hwang's Computer Arithmetic, Wiley, New York, 1979 is one of the best known.
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