5.4 Low-Power Design Tools

   

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Numerous EDA tools are available to help IC designers achieve low-power designs. These tools are classified into two main categories:

• Power-analysis and power-estimation tools

• Power-optimization tools

Power-estimation tools estimate the power of a specific design by identifying its high power consuming modules at early stages of the design. These tools give IC designers the ability to make high-level design decisions to reduce power or leave the design untouched based on a set of specific power constraints.

Power-optimization tools come into play after the decision is made by IC designers to reduce the power. These tools automatically implement appropriate power-minimization techniques discussed in earlier sections of this chapter, and they provide optimal low-power designs based on the level of design abstraction that they target. The EDA tools for low power are categorized based on the abstraction layer in which they operate . These layers are as follows :

• Behavior/System

• RTL/Architecture

• Gate/Logic

• Transistor /Switch

Figure 5.18 shows how low-power EDA tools are used in a low-power design.

Figure 5.18. Low-Power Design Flow Using EDA Tools

Table 5.4 provides a summary of some of the commercially available low-power EDA tools.

The two important issues to consider when evaluating the capabilities of low-power EDA tools are accuracy and speed of execution. Considering the role that each of these tools plays at different levels of design abstraction, there are always trade-offs between the accuracy and execution time. At the early stages of the design, IC designers need tools that are fast and capable of estimating or optimizing power easily for the entire design. Therefore, earlier in the design process and at high levels of design abstraction, the EDA tools need to be fast for analyzing the entire design. However, in later stages of design process, the tools need to be more accurate, and execution time becomes less crucial. Detailed information about some of these tools is available in Appendix A.

Table 5.4. Commercially Available Tools for Low-Power Design

EDA Tool	Abstraction Level	Function
DesignPower	RTL, Gate	Power Estimation
PowerCompiler	RTL, Gate	Power Optimization
PowerMill	Transistor	Power Estimation
PowerTheater Analyst	RTL, Gate	Power Analysis
PowerTheater Designer	RTL, Gate	Power Optimization
PrimePower	Gate	Power Analysis and Estimation

Behavior-Level Tools

This level of power estimation and optimization is the highest level of abstraction in design cycle, but is not supported by any commercial tools at present. Designers make spreadsheets based on various components , such as flip flops and memories in their design, and use power formulas to estimate the power.

RT-Level Tools

Register transfer, or architectural level, power estimation is a fast method that circuit designers can use to predict power consumption at the early stages of design hierarchy. RTL power-estimation tools can predict a circuit's power consumption using the number of transitions of different synthesis factors obtained from RTL simulations. This level of power estimation is less accurate compared to the other two levels defined earlier. However, it has two significant advantages that help designers to make design decisions at early stages of their design. These advantages are as follows:

• Faster runtime

• Power estimation early in the design cycle

The accuracy of this technique depends on the delay model used in the estimation tool.

Zero-delay model is the simplest model used in estimation tools. This model considers a value of zero for the delay of each gate. For simplification, the zero delay model disregards the glitching effects and calculates the circuit-node changes only once per clock cycle. This model does not provide realistic timing information about the gates in a design and underestimates the power in circuits.

Unit-delay model assumes a unique delay for all the gates in a circuit. Glitches in a design can be represented using this model. However, since the unit-delay model does not provide accurate timing for the gates, both underestimation and overestimation of power dissipation are anticipated.

Full-timing-delay model is the most accurate model for power estimation. Glitches can be perfectly represented in designs using full-timing-delay models. Therefore, no overestimation or underestimation of dissipated power is will occur.

Most RTL optimization tools automatically implement clock gating to synchronous registers in order to save power. Throughout the power-optimization period, the power information is updated continuously until the optimal low-power solution is achieved.

Examples of low-power estimation tools are DesignPower from Synopsys and PowerTheater Analyst from Sequence Design, Inc. The popular power-optimization tools are PowerCompiler from Synopsys and PowerTheater Designer from Sequence Design, Inc.

Gate-Level Tools

Gate- or logic-level power-estimation tools are less accurate compared to transistor-level tools but have considerable enhancement in runtime. These tools estimate power consumption due to the transitions made by every node in gate-level simulation. Gate-level power-estimation tools operate on a gate-level netlist, such as Verilog or VHDL, and calculate the power consumed at each node using Equation 5.5. The sum of all node powers represents the estimated power of circuit as shown in Equation 5.7.

Equation 5.7

This level of power estimation is more accurate than RTL estimation methods and is used in later stages of design hierarchy when the design is completed, synthesized , and simulated. Examples of these tools include PowerTheater Analyst and PrimePower.

Transistor-Level Tools

Transistor or switch-level power-estimation tools are very accurate. These tools can model each circuit element precisely and estimate power consumption within a few percentage points of precision. However, long runtime restricts their use to small designs. Transistor-level power-optimization tools automatically resize the transistors in a design to meet power requirements estimated by transistor-level power-estimation tools. They compute the slack time of each gate. For negative slacks, these tools upsize the transistors, and for positive slacks, they downsize each transistor. Also, signals with high-transition level are automatically assigned with short wires.

Although these tools are very accurate, they are not very popular among ASIC and SOC designers for the following two reasons. One is the long runtime that restricts their use to small circuits. The other is that most ASIC vendors do not provide transistor level netlists.

Examples of these tools include HSPICE and PowerMill from Synopsys Inc.

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