Warm Reset


Warm reset can be triggered by a hardware event, or system software may initiate a warm reset. Note that the system must not generate a warm reset when changing the frequency or width of a link. Specifically, if one side of the link has had its width or frequency changed, but not the other side, following warm reset, one side of the link would think the other is faster and/or wider than what it is actually programmed to be.

Warm reset is detected when PWROK is asserted (logic high) and RESET# is asserted (logic low). Warm reset differs from a cold reset in following ways:

  • The LinkWidthIn and LinkWidthOut values are not affected by a warm reset (i.e., these values persistent across a warm reset) and take effect following warm reset.

  • The LinkFrequency registers are persistent across a warm reset, and take effect after warm reset.

  • CAD values are driven to represent the updated link width, rather than the low-level values defined for cold reset.

Table 12-6 lists the state of the HT signals during a warm reset.

Table 12-6. Signal States During Warm Reset

Signal

State During Warm Reset

CLK

Toggling

CTL

Logic 0

CAD[n-1:0] (Updated width)

Logic 1's

CAD[31:n] (if present)

Logically undefined within electrical spec.

Following warm reset the same synchronization sequence (i.e. same as cold reset) is performed to initialize the transmit and receive clocks.

Warm Reset Generated by Software

The specification defines a bit in the HT bridge's HyperTransport Host Command CSR that provides a way for software to initiate warm reset on the secondary bus of an HT-to-HT bridge. Refer to Figure 12-20 on page 304. Specifically, this bit defines the type of reset that will be initiated on the secondary bus when software sets the Secondary Bus Reset bit of the Bridge Control register.

Figure 12-20. HyperTransport Host Command CSR

graphics/12fig20.jpg

The state of the warm reset bit only has meaning when software initiates a reset sequence. Actions taken during the reset sequence depends on the state of the warm reset bit as follows :

  • If warm reset is 1, PWROK will remain high and RESET# is asserted, causing a warm reset

  • If warm reset is 0, PWROK will be driven low along with the RESET# signal, causing a cold reset.

  • If not implemented, this bit is read-only and hardwired to 1.

It is the responsibility of the hardware to sequence PWROK and RESET# correctly.

Changing the state of the Warm Reset bit while the Secondary Bus Reset bit is asserted results in undefined behavior. Defined changes include:

  • Previously assigned UnitID's are forgotten and all UnitID's default back to zero.

  • Configuration Space Registers (CSR's) that are defined to be persistent through a warm reset do not go to their default state. Instead, their current state is maintained .

RESET# must be asserted for at least 1ms during a warm reset sequence.



HyperTransport System Architecture
HyperTransportв„ў System Architecture
ISBN: 0321168453
EAN: 2147483647
Year: 2003
Pages: 182

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