Trodden J., Anderson D. HyperTransport System Architecture / Chapter 11. Routing Packets

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HyperTransport System Architecture
Authors: Trodden J., Anderson D.
Published year: 2003
Pages: 83-84/182

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Chapter 11. Routing Packets

The Previous Chapter

The previous chapter described HyperTransport flow control , used to throttle the movement of packets across each link interface. On a high-performance connection such as HyperTransport, efficient management of transaction flow is nearly as important as the raw bandwidth made possible by clock speed and data bus width. Topics covered here include background information on bus flow control and the initialization and use of the HyperTransport virtual channel flow control buffer mechanism defined for each transmitter-receiver pair.

This Chapter

This chapter describes the rules governing acceptance, forwarding, and rejection of packets seen by HyperTransport devices. Several factors come into play in routing, including the packet type, the direction it is moving, and the device type which sees it. A related topic also covered in this chapter is the fairness algorithm used by a tunnel device as it inserts its own packets into the traffic it forwards upstream on behalf of devices below it. The HyperTransport specification provides a fairness algorithm and a hardware method for tunnel management packet insertion.

The Next Chapter

The next chapter describes the ordering rules which apply to packets associated with the three types of HyperTransport I/O traffic: PIO, DMA, and Peer-to-Peer. Depending on the whether compatibility with the full producer-consumer ordering model used in PCI is required or relaxed ordering is permissible, attribute bits in request and response packets may be set or cleared. These bits are defined by the requester and are used by devices in the path to the target, and within the target, to enforce proper ordering. HyperTransport applies dedicated sets of ordering rules for upstream I/O traffic, downstream I/O traffic, and the special ordering required of host bridges and in double-hosted chains. Refer to Chapter 20, entitled "I/O Compatibility," on page 457 for a description of the additional ordering requirements when interfacing HyperTransport to other compatible protocols (e.g. PCI , PCI -X, and AGP).

Packet Routing: Shared Bus vs. Point-Point Topology

Routing information in a shared bus topology such as PCI or PCI-X is somewhat simpler than in a point-point topology such as HyperTransport.

Shared Bus Routing

Referring to the PCI/PCI-X shared bus example illustrated in Figure 11-1 on page 258, it should be clear that if a transaction appears on the shared bus, all devices "see it" and have an opportunity to decode the address and command and claim the cycle. Devices other than bridges have no responsibilities for routing information to their neighbors. Also note that arbitration on a shared bus is simple because a single arbiter can manage the entire bus. In PCI/PCI-X, the arbiter is typically in the bus Host Bridge; the arbiter considers requests from each master, then grants the bus to each in turn , hopefully applying a reasonable fairness algorithm.

Figure 11-1. Routing: Shared Bus vs. HyperTransport Point-Point

graphics/11fig01.jpg

HyperTransport Point-Point Routing

In contrast to the shared bus approach, the HyperTransport topology distributes responsibility for routing and forwarding packets among all devices, with the exception of single-link end (cave) devices. For example, the tunnel peripheral device in Figure 11-1 on page 258 must observe a set of rules governing acceptance, forwarding, and rejection of packets moving both upstream and downstream. The end device in Figure 11-1 on page 258 is dependent on the tunnel to do this. Note that a benefit of a point-point bus is the elimination of shared bus arbitration. Packet transfer is subject only to flow control on each link.