Appendix Glossary of Terms

Address Map.

The 1.04 revision of the HT specification defines a 40-bit memory map. All resources which can be targeted with directed packets are mapped into this space. In addition, reserved portions of the memory map are used for special purposes, including IO accesses , broadcast messages, interrupts, configuration cycles, etc.

AGP (Accelerated Graphics Port).

A high-performance, point-to-point interface which connects a graphics adapter to the main memory controller in the Memory Controller Hub (MCH) or North Bridge (Host/PCI Bridge).

Atomic Read-Modify-Write Transaction.

A hybrid read and write operation issued from one source, targeting main memory. An Atomic RMW is guaranteed to complete without intervening accesses of the same location by any other device. This command is useful when a memory semaphore is being updated by one of the devices sharing it. HT supports two Atomic RMW variants: Fetch and Add and Compare and Swap.

Base Address Registers (BARs).

Device configuration registers that define the start address, length, and type of address space required and owned by a device. The type of space implemented will be either memory or I/O. The value written to this register during device configuration will program its address decoders to detect and accept accesses within the indicated range. Because HT memory maps IO accesses, an IO request in the Base Address Register will result in the assignment of a starting address in the memory map range reserved for IO.

Bit Time.

One half of a link clock period. As a double data rate (DDR) interface, HT CAD and CTL information is sent during each bit time, resulting in two bits transferred, per signal, per clock.

Bridge.

A device that provides a logical and electrical interface between two independent buses. Examples would be the bridge between the host processor bus and HyperTransport, a bridge between PCI/PCI-X and HT, or a bridge between two HT buses. Each secondary interface hosts a new bus (chain).

Broadcast Message.

A special case of a posted write request which is used to deliver a message to all devices that see it. There is no specific target; each device accepts it (based on the command type) and forwards it downstream. The end-of-chain device accepts the message, and drops it.

Broadcast Request.

See [Broadcast Message]

Bus Concurrency.

Separate transfers occurring simultaneously on two or more buses. Because HT is implemented with independent point-to-point connections instead of a shared bus, HT concurrency can occur within the same chain.

Byte.

8 bits of digital information.

Byte Mask.

In HT, there are no separate byte enable signals; data bus usage is implied in the command type and the mask/count field which accompanies request and response packets. For WrSized (byte) requests , a 32 bit "byte mask" precedes the 1-16 dword data packet and indicates valid bytes being sent ” much like byte enables in PCI.

Byte Read.

Sized read requests (RdSized) in HT carry a bit indicating whether the data to be transferred is in bytes or dwords. For byte reads, the maximum transfer size is one dword (four bytes); the mask field in the request indicates the valid bytes being transferred. Any byte combination is valid.

Byte Write.

Sized write requests (WrSized) in HT also carry a bit indicating whether the data to be transferred is in bytes or dwords. For byte writes , any combination of bytes within a 32-byte, address aligned group may be transferred. The count field in the request indicates the total dwords sent; valid bytes within those dwords are indicated in the 32-bit byte mask which precedes the data.

Cache.

A relatively small amount of high-speed Static RAM (SRAM) that is used by CPUs to keep copies of code/data information recently read from system DRAM memory. Data from internal CPU caches may be accessed at full internal clock speed, avoiding a bus cycle to main memory.

Cache Line.

When data is moved into or out of a cache, the transfer occurs in fixed amounts called cache lines. The size of a cache line is cache design dependent, but typically is 32, 64, or 128 bytes.

CAD Bus.

The CAD ( Command, Address and Data ) bus carries all information, control, and data packets between two devices on a link. There is one CAD bus in each link direction, and bus width ranges from 2 bits to 32 bits wide.

Capability Registers.

HT devices implement one or more sets of advanced capability registers to support features beyond basic PCI compliance. Capability register defined include: Host/Secondary interfaces, Slave/Primary interfaces, Interrupt Discovery and Configuration, Address Remapping, Revision ID, etc.

Cave Device.

A single-link HT device. These always reside at the end of a chain and are also referred to as end devices.

Chain.

In HT, a logical bus may be comprised of multiple devices daisy-chained together. At the top of the chain is a host bridge, in the middle there may be dual-link tunnel devices. At the end of a chain is a device with a single link connection to the chain. This may be a cave device, a tunnel device using only one interface, or the primary interface of a bridge to a new chain (bus).

Chain Down Error.

In HT, each device is required to track outstanding requests until a response is returned. A chain down error is said to have occurred if a link goes down between the time a non-posted request is issued and its response returns. A reset will flush any pending requests after a chain down error.

Chain Fail.

A chain fail occurs when a Sync flood or an event that can cause one is detected . Each device which detects the event sets the chain fail bit in its Error Handling register. The bit is cleared on reset.

Clocking Modes.

HT supports three clocking modes of a link receiver interface with respect to the corresponding transmitter: synchronous clocking, pseudo-synchronous clocking, and asynchronous clocking.

Coherency.

If the information resident in a cache accurately reflects the original information in DRAM memory, the cache is said to be coherent or consistent. In HyperTransport, transactions targeting DRAM main memory may either require action to guarantee coherency, or not. The coherent bit in WrSized and RdSized request packets indicates whether or not the host bridge must take coherency actions (cause a snoop of the CPU caches, etc.).

Coherent Bit.

See [Coherency]

Command Code.

Each HyperTransport control packet contains a 6-bit command code in the first byte. This information informs other devices of the intended operation and the format of the remainder of the packet. Some of the 6-bit command codes include options bits which may be used to indicate whether the packet is to travel in the isochronous channel, is posted or not, etc.

Compatibility Bit.

The compatibility bit (Compat) in an HT request is set by the host bridge to indicate the packet must be forwarded down the compatibility chain in the direction of the compatibility bridge where it will be accepted, regardless of the address it carries. The use of this bit provides compatibility with the South Bridge subtractive decoder in PCI systems where transactions which are otherwise unmapped in the system may be claimed by the subtractive decoder and forwarded to the compatibility bus (e.g. ISA).

Configuration Cycle.

A link transaction to read or write the contents of a device's configuration registers is called a configuration cycle. In HT, configuration accesses are performed using RdSized and WrSized requests targeting addresses reserved for configuration type 0 and type 1 cycles.

Configuration Space.

Each HT device is required to implement the 256 byte configuration space required of all PCI-compliant devices. Because PCI permits 256 busses in a system, 32 logical devices per bus, and 8 functions per device, the total configuration address space to reach all possible devices and functions is 16MB (256 busses x 32 devices x 8 functions x 256 bytes = 16MB). HT memory maps the entire configuration address space in a 32 MB reserved address range; the lower 16MB of the reserved range is for type 0 configuration cycles and the upper 16MB of the reserved range indicates type 1 configuration cycles.

Configuration Header Region.

The first one-fourth of the configuration space (64 bytes) has a well-defined format and is referred to as the configuration header region. The two key header formats are type 0 (non-bridge) and type 1 (HT bridges or bridges between HT and other compatible protocols (PCI, PCI-X, or AGP).

Consistency.

See [Coherency]

Control Packet.

Control packets include information, request, and response types. Information packets are used for local communication between the transmitter-receiver pairs on each link. Request packets may be 4 or 8 bytes, and are used to initiate transactions. Response packets are 4 bytes and are returned by the target of each non-posted request.

CRC.

In HT, a Cycle Redundancy Code (CRC) is used to assure the integrity of transmitted data. Starting after reset, each transmitter on each link interface calculates a 32-bit CRC value and periodically sends it to the corresponding receiver where it is checked against the value calculated as CAD packets arrive . CRC is calculated independently for each 8 bits of CAD width. The error handling strategy for handling CRC errors is programmable.

CRC Testing Mode.

HT provides a method for stress-testing CRC checking at the receiver. If both devices on a link support the CRC test mode, a transmitter can enter the CRC test mode under software control and generate dummy packets which are checked for CRC validity by the receiver, then dropped.

CTL Signal.

The link control (CTL) signal is driven by each transmitter to indicate to the receiver that control packet information is in transit over the CAD bus; when CTL is deasserted by the transmitter, a data packet is in transit. The receiver uses the CTL signal to demultiplex control and data packets.

Cycle Redundancy Code.

See [CRC]

Data Packet.

In HT, the data transfer payload is sent in data packets. All HT packets are multiples of four bytes and a data packet may contain from 1 to 64 valid bytes depending on the request type and transfer count that caused it.

Device.

A device is a physical IC package. In HT, a device may contain from one to eight independent logical functions, each of which may consume multiple Unit IDs. PCI compatible device types include host bus bridges, bridges from HT-to-HT (or HT-to-PCI/PCI-X), and tunnel and single-link peripherals.

Direct Memory Access ( DMA ).

A class of transactions in which the source is an IO device accessing main memory directly. Devices commonly using DMA transfers include disk adapters, graphics adapters, USB controllers, etc. DMA transfers relieve processors from much of the burden of large data transfers.

Disconnect.

A bus event in which a target forces a source to break off the transfer of data early because it cannot sink or source the next data in the time allowed by bus latency rules. HT uses flow control to assure that no packet is sent across a link which cannot be accepted in its entirety by the corresponding receiver; HT does not support a disconnect mechanism.

DHC.

See [ Double-Hosted Chain]

DMA.

See [Direct Memory Access]

Double-Hosted Chain.

A HT topology which includes a host bridge on both ends of a chain. One host bridge is designated the master host, the other is the slave host bridge. These topologies include two variants: sharing double-hosted chains and non-sharing double-hosted chains. Under software control, chain resources may be allocated to either bridge.

Double Word ( Dword ) Read.

Sized read requests (RdSized) in HT carry a bit indicating whether the data to be transferred is in bytes or dwords. For dword reads, any sequence of consecutive dwords in a 16 dword address-aligned group may be transferred. The count field in the request indicates the number of dwords being transferred.

Double Word ( Dword ) Write.

Sized write requests (WrSized) in HT carry a bit indicating whether the data to be transferred is in bytes or dwords. For dword writes, any sequence of consecutive dwords in a 16 dword address-aligned group may be transferred. The count field in the request indicates the number of dwords being transferred.

Doubleword ( Dword ).

Four bytes (32 bits) of digital information.

End Device.

A single-link HT device. These always reside at the end of a chain and are also referred to as cave devices or IO hubs.

End Of Chain ( EOC ).

Devices at the end of each HT chain have special responsibilities for handling mis-directed packets, including the return of responses for non-posted requests received in error. An end-of-chain device may be a single-link peripheral or a tunnel device which is either unconnected on one interface or has been programmed to act as an end-of-chain device.

End Of Interrupt ( EOI ) Message.

Certain interrupts (e.g. level sensitive, shared interrupts) may require an acknowledgement of servicing by the CPU. In HT, the EOI broadcast message is sent downstream to provide this confirmation. Each device that decodes the EOI message clears outstanding interrupts indicated in the IntrInfo field, and passes the message on to the next downstream device.

Error Handling.

HT defines a number of error types, including CRC, protocol, receive buffer overflow, end-of-chain, response, and chain down errors. Only the generation and checking of CRC errors is required. One or more logging bits in configuration space is defined for each supported error type, and the reporting method for each is programmable in software. Reporting methods include response with error bit set, fatal and non-fatal interrupts, and Sync flood.

Fairness Algorithm.

HT specifies a fairness algorithm that tunnel devices are required to observe when inserting their own packets into a packet stream that they are forwarding on behalf of devices below them.

Fabric.

The collection of devices in a HyperTransport topology, including a bridge to the host system.

Fatal Interrupt.

A fatal interrupt message is sent by a device which detects an error condition it may not be able to recover from. It is roughly equivalent to the non-maskable interrupt (NMI) seen in PCI.

Fence Request.

A request which is sent to a bridge and acts as a barrier to subsequent posted writes. Posted writes received before the Fence must be sent on to memory before later posted writes are processed by the bridge. Fence applies to posted writes from all transaction streams.

Flow Control.

A credit scheme in which each link receiver uses NOP packets to inform the transmitter of released space in virtual channel buffers. Flow control guarantees that no packet is sent by a transmitter that cannot be accepted in its entirety by the receiver.

Flush Request.

A non-posted request sent to a bridge which causes all previous posted writes from that source to be pushed to memory. A target done response is returned to the source when the flush operation is complete.

Functional Devices.

PCI-compatible devices, including HT, may support from one to eight logical entities called functions. Each function has its own configuration space and behaves as an independent logical device.

Header.

HT device functions implement the 256 byte PCI configuration space. The first one-fourth of configuration space is called the header, and two formats are used: the HT technology type 0 device header is for non-bridges; the HT technology type 1 bridge header is for HT-HT, HT-PCI, and HT-PCIX bridges.

Hierarchy.

In a topology based on point-to-point connections and bridges which add additional secondary busses (chains), the relative positions of devices upstream and downstream from each other is referred to the hierarchy; hierarchy must be taken into account when determining latencies, applying ordering rules, etc.

Hit.

Refers to a hit on the cache. This may result from a processor initiating a read or write to a cache, or from a host bridge submitting an address associated with an IO access of memory to the cache controller(s) for look-up. Actions taken by the system depend on the state of the cache line. In HT, transactions targeting main memory may or may not be submitted to caches for look-up, depending on the state of the coherent bit in the request packet.

Host Bridge.

A device that provides the bridge between the host processor's bus and the first HT chain. The bridge buffers information and provides protocol translation in both directions; it also acts as host to the HT chain below it. Note: In HT, the secondary bus interfaces of each HT-to-HT bridge or PCI(X)-to-HT bridge act as host bridge for their respective chains.

Host/Secondary Interface Block.

The advanced capability register block implemented in configuration space by bridges to manage a secondary bus. This set of registers would be implemented by a HT host bridge, HT-HT bridge, or PCI(X)-HT bridge for each secondary interface.

Idle State.

A transaction is not currently in progress on a link. In HT, the idle condition is indicated when NOP packets are transferred by each link transmitter. The NOP packets also contain flow control update information.

Information Packet.

The NOP and Sync/Error information packets are used for nearest -neighbor communication on each link. They are not forwarded to other links and are not flow-controlled. When sent by a transmitter, they must be accepted by the corresponding receiver.

Interrupt.

HT devices requiring service generate interrupts using messages. A WrSized request packet is sent upstream using an address range reserved for interrupt traffic. The method the host bridge uses for delivering them to the CPU(s) is implementation-specific.

Interrupt Acknowledge .

In x86-compatible systems, the host processor may respond to an interrupt request on its INTR input by generating an interrupt acknowledge transaction. If the system interrupt controller resides in (or below) the HT topology, the interrupt acknowledge cycle travels downstream through HT to the interrupt controller as a RdSized (byte) read request targeting the reserved IACK address range. The South Bridge or other component containing the interrupt controller later returns the vector of the highest priority interrupting device with the HT read response.

Interrupt Controller.

In many systems, interrupts from IO devices are gathered and prioritized by a motherboard interrupt controller (e.g. IOAPIC). While some systems would always implement an interrupt controller, it is not required in HyperTransport. HT defines an Interrupt Discovery and Configuration capability block for functions. Using this capability block, software can program individual devices with information required to manage each interrupt.

I/O Chain Initialization.

The sequence used to bring up the devices on an HT chain. Initialization starts at reset, and includes low-level link negotiation and synchronization by devices, sending of initial buffer release packets to establish flow control buffer size, followed by software configuration of device header and advanced capability registers.

I/O Hub.

A type of HT device used to perform one or more functions generally associated with a legacy I/O controller (e.g. South Bridge or ICH). An I/O hub may or may not reside at the end of a chain.

I/O Stream.

A collection of transactions in HT sourced by a single node and terminating at the same destination. HT ordering treats separate I/O streams independently.

Isochronous Traffic.

Traffic with special latency or bandwidth requirements. Devices which support isochronous packets give them priority over the standard posted request, non-posted request, and response virtual channels.

LDTREQ# Signal.

This open drain, wire or'd power management signal is bussed to devices supporting power management state changes. When asserted (low), the link is either active or being requested by device(s). If it is de-asserted, the link is inactive.

LDSTOP# Signal.

This signal is driven by the system management controller (e.g. South Bridge) and is used to enable and disable HT links during system state transitions. It is an input to HT devices which support the signal; when asserted, device transmitters finish sending any packets in transit and then start disconnecting from the link. After sending disconnect NOP packets, the transmitter shuts down its drivers. Receivers detecting the disconnect NOPs also may be shut down to save power. Upon deassertion of LDTSTOP#, devices commence reconnection to their links.

Link.

The connection between two HT devices. A link is comprised of two sets of high speed, unidirectional signals (CAD, CTL, CLK) and a single set of bussed, low speed signals: PWROK, RESET#, and optional LDTSTOP# and LDTREQ# signals.

Master Abort.

If an HT source attempts to perform a non-posted transaction with a target, and the response packet (with error and NXA bits set) is returned instead by an end-of-chain device, the source considers the event a master abort. This is equivalent to unclaimed PCI or PCI-X transactions which are characterized by no assertion of the DEVSEL# signal. The source sets the received master abort bit in its device configuration header Status register. It also may inform its driver of the event by generating an interrupt.

Miss .

Refers to a miss during a cache look-up. In HT, transactions targeting main memory may or may not be submitted to caches for look-up, depending on the state of the coherent bit in the request packet.

Multi-Function Devices.

A PCI-compatible physical device may have one to eight independent functions integrated within the package. A component that incorporates more than one function is referred to as a multi-function device.

Node.

A physical attachment to one end of an HT link.

Non-Sharing Double-Hosted Chain.

See [Double-Hosted Chain]

Ordering Rules.

HyperTransport defines upstream, downstream, and host ordering rules for packets moving through the topology. While packets in different I/O streams generally have no ordering relationships with each other, virtual channels within the same I/O stream follow either the full producer-consumer ordering model used in PCI, or may use optional relaxed ordering if strict ordering is not required.

Packet.

All information transmitted across each HT link is sent in multiples of 4-byte blocks called packets. The two classes of packets are Control and Data. Control packets include information, request, and response variants; data packets carry a payload of 1-64 bytes.

PCI.

See [Peripheral Component Interconnect]

Peer-to-Peer.

HT defines transaction types: programmed IO (PIO), direct memory access (DMA), and peer-to-peer. A peer-to-peer transfer is one in which one IO devices target one another directly, without involving main memory.

Peripheral Component Interconnect ( PCI ).

A widely accepted interconnect and bus transfer protocol which provides a relatively fast, plug-and-play, parallel bus used to connect high speed peripherals to each other and to main memory. The PCI specification also defines connectors which may used to support add-in cards. The PCI configuration and control methods are also used in newer PCI-compatible protocols including HT, PCI-X, and AGP.

Point-To-Point Signals.

Point-to-point signals provide a direct interconnect between two devices. These connections are simpler electrically than shared bus signals such as those found on PCI; if speed is required, they can be clocked faster. With only two devices, the arbitration latency which associated with multiple masters on a shared bus is also eliminated in point-to-point connections. HT is comprised of a series of point-to-point links.

Posted-Writes.

The immediate completion of write transactions through the use of dedicated write buffers at the receiver. Posted writes are fast because they do not require a response; they are considered complete by a sender as soon as they are accepted by the corresponding receiver. Because HT is comprised of a series of point-to-point connections, posted writes are critical to eliminating latencies in reaching the ultimate target. HT write request packets include a "posted" bit which indicates whether the request should be posted or not. Non-posted writes always result in the return of a target done response by the target.

PWROK Signal.

Used in conjunction with RESET# to indicate a cold or warm reset event on a chain. If PWROK is asserted with RESET#, warm reset is signalled; if PWROK is deasserted and RESET# asserted, cold reset is underway.

Primary Bus (Chain).

For bridge devices, the primary bus (chain) is the one in the direction of the host CPU.

Quadword ( Qword ).

Eight bytes (64 bits) of digital information.

RdSized Request.

See also [Double Word Read]

See also [Byte Read]

Read Request.

See also [Double Word Read]

See also [Byte Read]

Read Response ( RdResponse )

A control packet returned by targets of RdSized or Atomic RMW requests; the read response precedes the data packet and acts as a tag to assure delivery to the original source. In the event of an error, a read response carries NXA and error bits which are used to indicate the nature of the error. All requested data is sent after the read response, regardless of any error condition.

RESET# Signal.

As in PCI, HT hardware or software reset events may be either cold or warm. If PWROK is asserted with RESET#, a warm reset is indicated; if PWROK is deasserted and RESET# asserted, a cold reset is underway. Cold and warm reset have different implications on persistent areas of configuration space, including errors which may have been logged there prior to the reset.

Retry .

In some bus protocols (e.g. PCI), a target may signal "retry" to the initiator to indicate it cannot sink or source the first data in the time allowed by bus latency rules. HT uses flow control to assure that no packet is sent across a link which cannot be accepted in its entirety by the corresponding receiver; HT does not support a retry mechanism.

Request.

An HT control packet type used to initiate a transaction. Request packet size is four bytes or eight bytes, and carries attribute bits which may include I/O stream, target address, virtual channel, whether it should be posted or not, byte or dword data transfer, transfer size, coherency requirements, etc.

Routing.

HT devices accept, forward, or reject packets based on the type of packet, its transaction stream, and the direction it is moving. Basically, directed requests are routed on the basis of the 40-bit address field, responses are routed based on UnitID and the bridge bit state, and broadcast messages are accepted and forwarded by all devices which decode them. Flush and Fence requests are routed upstream to the host bridge based on the command type.

Scalability.

Depending on bandwidth needs, HyperTransport allows scaling of the CAD bus signal group width from 2-32 bits in each link direction. Asymmetrical CAD bus widths on a link is also permitted. The link clock frequency is also scalable from 200MHz-800MHz.

Secondary Bus (Chain).

For bridge devices, the secondary bus (chain) is the one away from the direction of the host CPU. In HT, bridge devices are permitted to support multiple secondary busses; each secondary bus has its own bus number and acts as host bridge to the devices on the chain below it.

SeqID [4:0].

See [Sequence ID]

Sequence ID.

Used to override general ordering rules. All request packets carrying the same 5-bit, non-zero sequence ID will be handled as being part of the same strongly ordered sequence by tunnels and bridges in the path to the target.

Sharing Double-Hosted Chain.

See [Double-Hosted Chain]

Sized Read.

See also [Double Word Read]

See also [Byte Read]

Sized Write.

See also [Double Word Read]

See also [Byte Read]

Slave.

A tunnel or cave device which implements the Slave/Primary Interface block advanced capability register set.

Slave Host Bridge.

See [Double-Hosted Chain]

Slave/Primary Interface Block.

The advanced capability register block implemented in configuration space by non-bridges to manage HT interfaces. The register set is used to configure each link, log errors, set up error reporting, etc.

Snooping.

The process of presenting transaction addresses to cache controllers so that a check can be made to see if the information being accessed is also resident in the cache(s). If a cache contains information from the target address, a "snoop hit" occurs. Depending on the cache line state, action may have to be taken to assure cache coherency. Cache snoops take time and affect performance; in HT, request packets targeting main memory include a coherent bit indicating whether coherency actions are required.

Source.

The HT node initiating a transaction.

Source Tag.

A 5-bit field in request packets used to uniquely identify one of the 32 outstanding non-posted transactions allowed for one I/O stream.

SrcTag [4:0)].

See [Source Tag]

Stale Cache Line.

When caches are in use, there always is a hazard that a local cached copy may become stale if the memory location that sourced it is modified by another CPU or I/O device, or that memory may become stale if a cache line is modified and not written back. It is a system responsibility to use snooping or other mechanisms to guarantee that both of these cases are avoided.

Subordinate Bus Number.

The highest numbered bus (chain) below a bridge. A bridge contains three bus number registers which are programmed at boot time: primary bus number, secondary bus number, and subordinate bus number. These bus number registers are used to help the bridge claim/pass configuration transactions.

Subtractive Decode.

In x86 compatible systems, the PCI-to-expansion bus bridge (South Bridge) may claim transactions not accepted by other devices on the PCI bus. This is permitted because a non plug-and-play expansion bus (e.g. ISA) may host devices which own addresses not otherwise mapped in the system. For compatibility, HT also supports a subtractive decoder. Packets sent downstream by a host bridge with the Compat bit set are routed to the subtractive decoder, where they are accepted and forwarded to the compatibility bus.

Sync Flood.

A drastic method of reporting errors in which a device transmits Sync packets continuously until reset occurs. Each device on the chain that detects the Sync flood repeats the pattern on all links. A reset is required to recover from a Sync flood. Sync flood is analogous to SERR# on a PCI bus.

Sync Packet.

A control packet generated on each link interface during initialization to synchronize devices. It also is issued during Sync flood error reporting.

System Management.

HT supports a number of x86-compatible system management (SM) features. System management functions make use of system management messages sent to and from the system management controller (typically in the South Bridge), and the two SM signals: LDTREQ# and LDTSTOP#. SM functions include generating special cycles and disconnecting and reconnecting links.

Target.

A generic term used to indicate the ultimate destination in a transaction. Tunnels and bridges in the target path forward packets along. In HT, directed request packets are accepted by the target device when it decodes the address field. Some packets are accepted by a host bridge target based on the command type rather than a specific address (Flush, Fence). Finally, broadcast messages target all devices that see them.

Target Abort.

If an HT source attempts to perform a non-posted transaction with a target and the response packet returns with the error bit set and NXA bit cleared, the source considers the event a target abort. This is equivalent to the target abort in PCI which is characterized by the target asserting STOP# and de- asserting DEVSEL#. The source sets the received target abort bit in its device configuration header Status register. It also may inform its driver of the event by generating an interrupt.

Target Done ( TgtDone ) Response.

A control packet returned by the target of a non-posted write request or a Flush request. The TgtDone response acts as a tag to assure delivery to the original source. The response may indicate normal completion or that an error occurred at the target or at an end-of-chain device.

Transaction.

A sequence of packets accomplishing a transfer of information (e.g. read request packet followed by a read response and data packet)

Transaction Stream.

See [I/O Stream]

Tree.

A HT chain with at least one bridge device. This results in more than one system chain (bus).

Tunnel Device.

A dual-link, non-bridge HT device which implements an internal peripheral function and is capable of forwarding traffic on behalf of other devices in the chain. Tunnels are the basic building blocks in HT chains.

Type One Configuration Access.

PCI compatible devices recognize two types of configuration cycles. The type one configuration access is used to indicate a cycle which has not yet reached the bus hosting the target device. Only bridges accept type 1 configuration cycles, and then only to pass them either upstream or downstream based on bus number. HT memory maps type 1 configuration cycles into the upper half of the address range reserved for configuration cycles.

Type Zero Configuration Access.

The type zero configuration access is used to indicate a cycle which has reached the bus hosting the target device. Upon decoding a type 0 configuration cycle, a device compares the device number field with its own. If the device number matches, it accepts the type 0 configuration cycle and uses the function and dword offset fields to access the proper internal configuration space location. HT memory maps type 0 configuration cycles into the lower half of the address range reserved for configuration cycles.

Unit ID.

A logical entity within a node. In HT, a functional device is permitted to consume multiple UnitIDs; packets from each UnitID are considered as independent I/O streams.

Virtual Channel ( VChan ).

For ordering purposes, HT defines three required virtual channels: posted requests, non-posted requests, and responses. Each receiver maintains a pair of flow control buffers for each virtual channel, one for command information and one for data associated with it. If isochronous traffic is supported, devices implement another set of six flow control buffers.

Word.

Two bytes (16 bits) of digital information.

Write Request.

See also [Double Word Read]

See also [Byte Read]

WrSized Request.

See also [Double Word Read]

See also [Byte Read]