Ethernet Interface

While there are a few processor chips that include a portion of the Ethernet interface on the chip, its still more common to find the Ethernet interface on a separate device. Like the serial port, the Ethernet interface is partitioned into two layers (protocol and physical). The protocol layer is implemented as a single block called the Media Access Layer (MAC). The physical layer consists of two blocks: a PHY and a transformer. It is becoming more common to see the PHY and Ethernet controller integrated into one device, but the transformer is still separate; hence, the Ethernet interface can consist of two or three distinct devices.

The Ethernet controller is the portion of the interface that does the packet-level work. For incoming packets, it verifies that the incoming frame has a valid cyclic redundancy check (CRC), ignores packets that do not match a specified MAC address, organizes the incoming frames as packets that can be retrieved by the CPU (usually through either a FIFO or DMA transfer), and generates interrupts based on various configuration parameters established by the driver. For outgoing packets, the Ethernet controller calculates the CRC, transfers data from memory to the PHY, adds padding to small packets, and interrupts the CPU to indicate that the packet has been sent.

The PHY takes care of the lowest level of the interface protocol. It is responsible for various parameters (like bit rate) specific to the environment.

The transformer provides isolation and electrical conversion of the signals passed over the cable.