Chapter 16. Support for NUMA and CMT Hardware


Contributions by Bart Smaalders, Eric Saxe, and Jonathan Chew

Sun historically built symmetric multiprocessor (SMP) machines in which all of memory was seen as a single pool, equidistant in terms of latency from the set of independent, identical CPUs. Thus, the memory hierarchy from the core of the CPU through the various on- and off-chip caches, buses, etc., to main memory was identical for all the CPUs in the machine. In addition, any components that were shared were shared by all the CPUs in the same manner.

Newer systems depart from this relatively straightforward architecture in two fundamental ways. The first type are machines in which some memory is closer to some CPUs than others. These are known as NonUniform Memory Access (NUMA) machines. The second type are machines in which some of the CPUs share various processor components and caches. This is referred to here as chip multithreading (CMT).

The Memory Placement Optimization (MPO) feature and CMT optimizations allow Solaris OS to support hardware with asymmetric memory hierarchies, such as cache coherent NUMA (ccNUMA) systems and systems with chip-level multi-threading and multiprocessing. Solaris runs on both NUMA and CMT machines and can further optimize performance by being locality aware (that is, Solaris knows which CPUs and memory are close to each other) and CMT aware (Solaris is aware of which logical CPUs share caches, data paths, and other processor facilities).




SolarisT Internals. Solaris 10 and OpenSolaris Kernel Architecture
Solaris Internals: Solaris 10 and OpenSolaris Kernel Architecture (2nd Edition)
ISBN: 0131482092
EAN: 2147483647
Year: 2004
Pages: 244

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