Index_C

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C

Cache Manager, Windows NT, 368

Catalog manager, 93

CD-ROM drives, 41

Central moments, 132, 158–59

Central processing unit. See CPU

Central server model, 234–40

adaptation, 235

analysis, 345–50

defined, 234–35

exponential service time distributions, 235

illustrated, 234, 346

See also Computational methods

Chebyshev's Theorem, 161–63

Checkpoints, 488

Chi-square distribution, 232

Chi-square test, 231, 232

Client/server policies, 81

Closed networks, 219–24

arbitrary, 222

state transition rate diagram, 221

three-stage, 219, 220

See also Queuing networks

CODASYL database language, 13

Colored Petri nets, 300–301

colored tokens, 300

defined, 300

See also Petri nets

Combinations, 144

Combined simulation modeling, 260–61

Common bus architecture, 10, 61

Communication lines, 468

Communications manager, 97

Compaction, 75–76

Complex instruction set computer (CISC), 7

Computational methods, 233–49

central server model, 234–40

mean value analysis, 234

operational analysis, 233

types of, 233–34

See also Queuing networks

Computer architectures, 9–10, 59–62

analysis of, 345–60

central I/O controller, 60

common bus, 10, 61

defined, 9

dual bus, 10, 61–62

illustrated, 9

memory-mapped, 60–61

Neumann, 59

See also Architectures

Computer systems

architectures. See Architectures

building blocks, 4, 41

with communications subsystem, 56

defined, 2–3

design, 23–24

illustrated, 3

interconnection, 38

multiprocessor, 55–56

multiuser, 11

research, 23

Computer system support software architecture, 62–92

database management system, 83–92

fault detection/recovery, 82–83

network control software, 79–82

operating systems, 64–79

Concurrency, 292

control manager, 95

Petri net modeling, 292

Conditional probability, 146–48

defined, 142

densities, 154, 155

space Venn diagram, 147

See also Probability

Confidence intervals, 230

defining, 230

percent, 231

for variance, 231

Configuration model, 447

Continuous random variables, 150

Continuous simulation modeling, 258–60

Control events, 479

Control unit, 42, 43

Cost, modeling, 334

Counting process, 180

CPU, 4, 62

ALU, 5

architectures, 5–6, 42–49

cycle of busy and idle, 350

cycles, 352

defined, 5, 41

interrupts, 50

memory access, 7, 40

processing capacity, 346

registers, 42–43, 63

scheduling, 384–86

service rate, 347

speed, 110

utilization, 375

Cyclic redundancy check (CRC), 474

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