D.9 System Control Registers

Most computer architectures contain a psr (processor status) register as a single place where an operating system and hardware can keep track of the most critical aspects of machine state. It is the highest locus of control of the machine by an operating system.

For the Itanium architecture, bits <5:0> of the psr are synonymous with the user mask (Section D.7).

Bits <23:0> of the psr are called the system mask, and special instructions are provided to reset (rsm) or set (ssm) groups of bits in that 24-bit segment. For example, bit <14> permits an operating system to enable and disable hardware interrupts.

A privileged mov instruction can modify bits <31:0> of the psr. For example, a debugger program can set bit <24> to enable data and address breakpoints.

Bits 32 and beyond are a region that includes bits <33:32> for privilege level. Of the four possible privilege levels, Linux uses only levels 0 (kernel level) and 3 (user level), but other operating systems could use all four rings of privilege level. Bits 32 and higher of the psr are indirectly modified during machine state transitions.

The Itanium architecture includes several additional categories of specialized registers whose details lie well beyond the scope of this book:

• control registers

• region registers

• protection key registers

• translation lookaside buffer

• debug breakpoint registers

• performance monitor configuration registers

Such registers are visible to privileged code in operating systems, and privileged instructions are usually needed to access them.