Chapter 12. Parallel Operations

Previous chapters have discussed nearly all of the nonprivileged Itanium instructions that operate on 64-bit integers or double-precision floating-point values. Those instructions comprise the fundamental set of operations that one expects of a processor design with a 64-bit datapath.

When a new architecture with a wider datapath becomes available, it takes time for the industry to take advantage of the new width. We have accorded preferential treatment to full-width instructions, which should in our view be very important in applications developed for the Itanium architecture over its lifetime.

In order to optimize special, but important, legacy circumstances, the Itanium architecture supports multiwidth load and store instructions that move bytes, words, and double words between memory and right-justified storage in the integer registers. Similarly, the cmp4 instruction specifically supports control of program flow based on testing 32-bit integer data.

Because of the way sign extension works for integers in two's complement representation, an architecture does not need to provide separate instructions to add bytes, words, or double-words. Historically, some CISC architectures have included arithmetic instructions for various widths of data, usually because a memory reference could be involved for a source or destination operand. RISC-like load/store architectures, by contrast, have sometimes not provided arithmetic or logical instructions for data narrower than the width of the datapath.

This chapter considers instructions with a different sort of variability, where operations on narrow data values packed into 64-bit integer or 82-bit floating-point registers execute in parallel. Hence the Itanium designers regard these to be parallel instructions.

We mention in Chapter 13 some of the ways that computer architectures have been extended after their initial design and introduction as marketed products. In particular, many instances of so-called multimedia extensions to instruction sets could be cited, such as those for the PA-RISC 2.0 architecture and the MMX^® and SSE extensions for the IA-32 architecture. The success of those extensions provided the motivation for similar parallel instructions in the Itanium architecture; we outline these instructions in this chapter.