| In a mainframe instruction stream, the next instruction is pointed to by the program status word (PSW). The current instruction is the only instruction according to the architecture. Everything else is considered to be data. Until the current instruction completes and the PSW changes its address, we can never be sure of what the next instruction is. What is the program status word? The PSW in each CPU contains information required for the execution of the currently active program. In the z/Architecture, it is 128 bits long and includes the instruction address, condition code, and other control fields. There are different ways that a PSW can get the address of the next instruction: If this instruction is not a branch, then add the length of the current instruction to the PSW to get the next address. If this instruction is a branch, then the resolved address of the branch is put into the PSW and that instruction is fetched.
The PSW governs more than what the next instruction is. It is also responsible for determining what addressing mode the mainframe should run in, as we explain in the next section. 21.3.1 Mainframe multimodality The addressing scheme of the mainframe has evolved over the years, beginning with 24-bit real addressing for S/360. Subsequently, as more storage space was needed by applications and operating systems, 31-bit addressing and, more recently, 64-bit addressing were introduced. The zSeries architecture provides for two schemes of floating-point arithmetic: Hexadecimal floating-point arithmetic, which uses the hexadecimal (radix-16). Binary Floating Point (BFP), which conforms to the IEEE standard for binary floating-point arithmetic, allows you to use IEEE floating-point instructions and introduces interoperability between zSeries and other platforms. Thus, programs can be migrated to and from workstations and any other platforms with different architectures, provided that they conform to the IEEE floating-point arithmetic standard.
21.3.2 The PSW bits A zSeries can operate with one of three addressing schemes: 24 bits, 31 bits, or 64 bits. With 24-bit addressing, you have the ability to address 16MB, with 31-bit you can address 2GB, and with 64-bit you can address 16EB. The addressing mode (how many bits to be used for addressing) is governed by bit 31 (the extended addressing mode bit) and bit 32 (the basic addressing mode bit) of the PSW. See Table 21-4. Table 21-4. The PSW controls addressing modePSW bit 31 | PSW bit 32 | Addressing mode |
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0 | 0 | 24-bit | 0 | 1 | 31-bit | 1 | 1 | 64-bit |
Addresses computed for 24- and 31-bit addressing mode have 40 or 33 zeroes, respectively, appended to the left to form a 64-bit address. So the resulting logical real and absolute addresses are always 64 bits long on the zSeries. The other bits in a PSW are described in Table 21-5. Table 21-5. Description of the bits in a PSWBit number | Description |
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S/390 | zSeries |
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0 | 0 | Reserved (must be 0); otherwise, a specification exception occurs. | 1 | 1 | Enables Program Event Recording (PER). PER is used to facilitate debugging, in particular, single stepping. | 2 4 | 2 4 | Reserved (must be 0). | 5 | 5 | Enables dynamic address translation (DAT). | 6 | 6 | Input/Output interrupt mask | 7 | 7 | Input/Output interrupt mask | 8 11 | 8 11 | PSW key used for complex memory protection mechanism (not used under Linux). | 12 | 12 | 1 on s/390; 0 on z/Architecture | 13 | 13 | Machine Check Mask, enables machine check interrupts. | 14 | 14 | Enables wait state. Stops the processor except for interrupts. | 15 | 15 | Enables problem state (if set to 1, certain instructions are disabled). All Linux user programs run with this bit on. | 16 17 | 16 17 | Address Space Control 00 Primary space mode. The Linux kernel currently runs in this mode, CR1 is affiliated with this mode and points to the primary segment table origin. 01 Access register mode. This mode is used in functions to copy data between kernel and user space. 10 Secondary space mode. Not used in Linux. 11 Home Space Mode. All user programs run in this mode.
| 18 19 | 18 19 | Condition codes (CC) | 20 | 20 | Fixed-point overflow mask; if 1=FPU exceptions for this event occur (normally 0) | 21 | 21 | Decimal overflow mask; if 1=FPU exceptions for this event occur (normally 0) | 22 | 22 | Exponent underflow mask; if 1=FPU exceptions for this event occur (normally 0) | 23 | 23 | Significance mask; if 1=FPU exceptions for this event occur (normally 0) | 24 31 | 24 30 | Reserved, must be 0. | | | 31 | Extended Addressing Mode | | | 32 | Basic Addressing Mode. Used to set addressing mode. | 32 | | 1 = 31-bit addressing mode; 0 = 24-bit addressing mode (for backward compatibility). Linux always runs with this bit set to 1. | 33 64 | | Instruction address | | | 33 63 | Reserved, must be 0. | | | 64 127 | Address In 24-bit mode, bits 64 103=0, bits 104 127 are the address. In 31-bit mode, bits 64 96=0, bits 97 127 are the address.
Note: Unlike 31-bit mode on S/390, bit 96 must be zero when loading the address with LPSWE; otherwise, a specification exception occurs. LPSW is fully backward compatible. |
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