The Intel Itanium

Like the Alpha, the Itanium is a 64-bit design. Its strategy for supporting complex instructions like those found on the VAX is quite similar to the Alpha approach.

The Intel Itanium is an Explicitly Parallel Instruction Computing (EPIC) design rather than a RISC design. However, some features of the Itanium are similar to a RISC architecture, as the term is used in this book. Namely, having relatively few instructions easily executed in parallel.

Just as with the Alpha architecture, some features required by OpenVMS are not supported by Itanium as native features. However, Itanium supports the copying of PALcode procedures from firmware to memory, providing a solution. It has also been written that some of these functions will be written into the Itanium version of OpenVMS itself, rather than in firmware. Although not all of the details are available as of this writing, one or both of these techniques will likely be employed.

In many ways, the porting of OpenVMS to the Itanium architecture will be less challenging than the previous port from VAX to Alpha because of similarities between the Alpha and Itanium hardware designs.

Like Alpha, Itanium will support multiple operating systems and provide support for both big-and little-endian data types, even though some aspects of instruction coding are little-endian only. The Itanium also supports 32-and 64-bit instruction sets, although this feature will likely be of more use to other operating systems than to OpenVMS.

Those features of OpenVMS that now support 64-bit addressing can be ported directly to Itanium. The Itanium architecture also provides four access modes (called "Privilege Levels" in Itanium nomenclature). OpenVMS requires four access modes, a feature found on relatively few CPU architectures, many of which supply only two modes.