| In a virtual memory system, pages are mapped from one set of addresses, virtual addresses, to another set, physical addresses. Each time the processor accesses memory, it does so using a virtual address. This address then gets translated to a physical address. This mapping takes place in units of pages. When a program addresses a virtual address, that address is first broken up into a virtual page number and an offset into that virtual page. The virtual page is then translated into a physical page. It's possible that the virtual page might be on disk rather than in physical memory. In this case, a page fault is generated and the page must then be brought in from disk to memory. In this section we look at how addresses get translated. The case where data is resident on disk rather than in physical memory is covered in Chapter 6. PA-RISC processors operate in one of two modes: narrow or wide. PA-RISC 1.1 processors are always narrow, and they operate on 32-bit addresses. PA-RISC 2.0 processors can be narrow or wide at any time depending on the setting of the W-bit in the PSW. Because the addresses are handled differently in these two cases, we look at both possibilities. We also look at the memory layout for both kernel mode and user mode. Recall that on a PA-RISC 1.1 system, the kernel and user applications are always narrow (32-bit). On a PA-RISC 2.0 system, the kernel can be narrow or wide (64-bit); on a wide kernel, applications can be either narrow or wide. Virtual Memory Layout, Narrow Mode As discussed, the entire set of virtual memory is divided into spaces. Every address is made up of a space and an offset into that space. In narrow mode, we use a 32-bit offset into a space, which means that every space is 232 or 4 GB in size. This 4 GB is in turn divided into four quadrants of 1 GB each. Each process on the system has four quadrants of address ranges that it can use. This doesn't mean that it has 4 GB of memory set aside just that it has that many unique addresses that it can access. However, these four quadrants are not necessarily in the same space. For example, a process might have quadrant 1 from space 0x123, quadrant 2 from space 0x234, quadrant 3 from space 0x345, and quadrant 4 from space 0x456. At the same time, some other process might have its quadrant 2 taken from space 0x123. To put this another way, each space is divided into four quadrants, and each quadrant belongs to a different process. The reason for this will become apparent when we talk about explicit and implicit addressing. The quadrants are determined by simply dividing the space into four equal pieces as determined by the upper two bits of the offset. Table 1-2 shows how address ranges map to quadrants. Table 1-2. Quadrants in 32-Bit ModeQuadrant | Virtual Address Range |
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Quadrant 1 | 0x00000000 to 0x3fffffff | Quadrant 2 | 0x40000000 to 0x7fffffff | Quadrant 3 | 0x80000000 to 0xbfffffff | Quadrant 4 | 0xc0000000 to 0xffffffff |
Virtual Memory Layout, Wide Mode In wide mode, the virtual memory concepts are the same as in narrow mode, but the register sizes are different and the calculations are done differently. The PA-RISC 2.0 architecture allows for space registers of up to 64 bits, although all current implementations us 32-bit space registers. Of these 32 bits, only the upper 22 bits are used; the lower 10 bits are always zero. General registers, which are used for the offset, are 64 bits wide. However, only the lower 42 bits are used for the offset. Like in narrow mode, the two highest bits indicate the quadrant. The result is that each quadrant is 4 TB, and each space is 16 TB. Table 1-3 shows how address ranges map to quadrants. Table 1-3. Quadrants in 64-Bit ModeQuadrant | Virtual Address Range |
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Quadrant 1 | 0x00000000 00000000 to 0x000003ff ffffffff | Quadrant 2 | 0x40000000 00000000 to 0x400003ff ffffffff | Quadrant 3 | 0x80000000 00000000 to 0x800003ff ffffffff | Quadrant 4 | 0xc0000000 00000000 to 0xc00003ff ffffffff |
32-Bit Address Space Layout Figure 1-5 shows the layout of memory in both 32-bit user mode and 32-bit kernel mode. Thirty-two-bit kernel mode is used only on PA-RISC 1.1 systems. On a PA-RISC 2.0 system, the kernel itself is always in 64-bit mode. Applications on a PA-RISC 2.0 system can be either 32- or 64-bit applications. On a PA-RISC 1.1 system, applications are always in 32-bit mode. Figure 1-5. 32-Bit Address Space Layout 
64-bit Address Space Layout Figure 1-6 shows the layout of memory in 64-bit mode, both for the kernel and for 64-bit user applications. One of the requirements for the 64-bit user mode is that a 64-bit application must be able to share memory with a 32-bit application. This is called mixed-mode access. In order to accommodate mixed-mode access, an area is set aside in quadrant 1 of the 64-bit layout. This area, starting at the 2 GB offset, corresponds with the beginning of quadrant 3 in 32-bit mode (also at the 2 GB offset). Figure 1-6. 64-Bit Address Space Layout 
Explicit and Implicit Pointers, Narrow and Wide Mode When operating in narrow mode, we have to work with a 16-bit space ID and a 32-bit offset for a total of 48 bits. For performance reasons, it is desirable to have a method of specifying an address in a single 32-bit register. For this purpose, PA-RISC uses the concept of a short pointer. A short pointer uses the upper two bits of the register to specify a space register and the remaining 30 bits to specify an offset. Recall also that those upper two bits indicate the quadrant in which an address resides. Table 1-4 shows the relationship between the high-order bits of an address, the space register used to address it, and the quadrant. Table 1-4. Space Registers and QuadrantsBits 0 1 | Space Register | Quadrant |
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00 | SR4 | Quadrant 1 | 01 | SR5 | Quadrant 2 | 10 | SR6 | Quadrant 3 | 11 | SR7 | Quadrant 4 |
As an example, the short pointer 0x40000782 refers to offset 0x782 in the space pointed to by space register 5. Another way of saying this is that 0x40000782 is in quadrant 2, which uses space register 5. In wide mode, our short pointers are 64 bits long. We still use the first two bits to indicate the space register or quadrant, as described in Table 1-4. The following 20 bits in the short pointer are always zero, followed by 42 bits of offset. This gives us the address range of 4 TB in a quadrant. For example, the address 0x40000001'201a39c3 is in the space pointed to by space register 5 at offset 0x1201a39c3. Address Swizzling Address swizzling is the process of converting a 32-bit address to a 64-bit address. When a 32-bit application is running on a 64-bit kernel, any addresses passed to the kernel must be swizzled to 64-bits. This process simply involves copying the upper 2 bits of the 32-bit address into the upper 2 bits of the 64-bit address, zeroing out the next 32 bits of the 64-bit address, and copying the lower 30 bits of the 32-bit address into the lower 30 bits of the 64-bit address. See Figure 1-7. Figure 1-7. Address Swizzling 
This process extends the 32-bit value to a 64-bit value while maintaining the correct quadrant. Note that this happens only for addresses, not for arithmetic values, which implies that the kernel must know that a value passed to it is meant to be an address. Global Virtual Addresses PA-RISC 2.0 introduced the concept of a Global Virtual Address (GVA). The GVA is a combination of the space and offset values, which results in a 64-bit unique address. In narrow mode, the space value is 32 bits long and the offset is 32 bits. We simply concatenate these two values to get a 64-bit GVA. For example, if we have an address of 0x3120.0x7ff33aeb, the GVA is just the concatenation of the two: 0x00003120'7ff33aeb. In wide mode, recall that we use a 32-bit space register, but only the upper 22 bits are used; the lower 10 bits are always zeroes. The offset is a 64-bit register, but the upper 22 bits are zeroed, and only the lower 42 bits are used. This allows us to concatenate the 22 bits of space register and 42 bits of offset to give a 64-bit GVA. We simply OR the 32-bit space register value with the upper 32 bits of the offset to get the 64-bit GVA. For example, if we have an address of 0x624b400.0x3ff'ff7c34e8, the resulting GVA is 0x0624b7ff'ff7c34e8. This 64-bit GVA is used as the basis for address translation. In the next section we see how the 64-bit GVA is translated to a physical address. | 