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Random-access memories provide a large number of storage elements in a single integrated circuit package. Static RAMs are based on a storage element constructed from cross-coupled inverters. These devices tend to be very fast. Dynamic RAMs are based on a single transistor storage element. They have higher capacity than SRAMs but longer access times.
Counters are an important class of sequential circuits, not only because they count events but also because they can be used to generate a periodic sequence. This has important implications for controller design, which we will examine in more detail in the next chapter.
We introduced a design procedure for mapping a state transition diagram, describing the count sequence, into actual hardware. The steps involved deriving the state diagram from the written specification for the counter, deducing a state table from the diagram which tabulates current and next states, expressing each next-state bit as a combinational logic function of the current-state bits, and remapping these next-state functions according to the kind of flip-flop chosen as a storage element. Excitation tables provide the information for remapping the next-state truth tables into truth tables for the selected flip-flops' inputs.
In general, J-K flip-flops yield counter implementations with the fewest gates. However, we often choose D flip-flops because of the simplified design procedure. No remapping step is necessary, and fewer wires are needed to control a D flip-flop.
Because real hardware does not necessarily come up in a known state, we described the concept of self-starting counters. Self-starting design methods can be used to get a counter
We presented counters without a global clock, asynchronous counters, and pointed out that their use should be avoided. We also demonstrated the advantages of counters with synchronous load and clear inputs, especially for the design of counters with starting or ending offsets.
In the final section, we looked at the timing behavior of a typical SRAM component in more detail. The important performance metrics are the memory access time and the memory cycle time. In addition, we introduced a simple memory controller design to illustrate the "glue" logic that must surround a RAM subsystem to interface it to the rest of the digital system.
We are now ready to study the design of more general circuits that follow a prescribed sequence other than the counters we have studied up to now. These finite-state machines will be the topic of the next chapter.
Perhaps the best way to learn about digital components is to study the relevant data books. For example, Cypress Semiconductor's CMOS/BiCMOS Data Book, San Jose, CA, 1989, describes their product line of very fast CMOS SRAMs in considerable detail.
An excellent survey and tutorial on memory system design using general-purpose and special-purpose RAMs can be found in Jean-Daniel Nicoud's paper "Video RAMs: Structure and Applications," which appeared in IEEE MICRO
For a system-level perspective on interfacing hardware to memory systems, see M. Slater's textbook Microprocessor-Based Design, published by Prentice-Hall in 1989.
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This file last updated on 07/14/96 at 16:36:05.
Chapter Review
In this chapter, we have focused on a variety of sequential circuits used mostly as storage elements: registers, counters, and RAMs. We saw how to construct registers for storage and shifting from simple D-type flip-flops sharing common clock lines.Random-access memories provide a large number of storage elements in a single integrated circuit package. Static RAMs are based on a storage element constructed from cross-coupled inverters. These devices tend to be very fast. Dynamic RAMs are based on a single transistor storage element. They have higher capacity than SRAMs but longer access times.
Counters are an important class of sequential circuits, not only because they count events but also because they can be used to generate a periodic sequence. This has important implications for controller design, which we will examine in more detail in the next chapter.
We introduced a design procedure for mapping a state transition diagram, describing the count sequence, into actual hardware. The steps involved deriving the state diagram from the written specification for the counter, deducing a state table from the diagram which tabulates current and next states, expressing each next-state bit as a combinational logic function of the current-state bits, and remapping these next-state functions according to the kind of flip-flop chosen as a storage element. Excitation tables provide the information for remapping the next-state truth tables into truth tables for the selected flip-flops' inputs.
In general, J-K flip-flops yield counter implementations with the fewest gates. However, we often choose D flip-flops because of the simplified design procedure. No remapping step is necessary, and fewer wires are needed to control a D flip-flop.
Because real hardware does not necessarily come up in a known state, we described the concept of self-starting counters. Self-starting design methods can be used to get a counter
(eventually) into a known, valid state.We presented counters without a global clock, asynchronous counters, and pointed out that their use should be avoided. We also demonstrated the advantages of counters with synchronous load and clear inputs, especially for the design of counters with starting or ending offsets.
In the final section, we looked at the timing behavior of a typical SRAM component in more detail. The important performance metrics are the memory access time and the memory cycle time. In addition, we introduced a simple memory controller design to illustrate the "glue" logic that must surround a RAM subsystem to interface it to the rest of the digital system.
We are now ready to study the design of more general circuits that follow a prescribed sequence other than the counters we have studied up to now. These finite-state machines will be the topic of the next chapter.
Further Reading
Just about any textbook on digital design will describe register and counter components and design strategies that employ them. It is more difficult to find good descriptions of memory components. J. Wakerly, Digital Design: Principles and Practices, Prentice-Hall, Englewood Cliffs, NJ, 1990 and Johnson and Karim, Digital Design: A Pragmatic Approach, PWS Publishers, Boston, 1987, are notable exceptions.Perhaps the best way to learn about digital components is to study the relevant data books. For example, Cypress Semiconductor's CMOS/BiCMOS Data Book, San Jose, CA, 1989, describes their product line of very fast CMOS SRAMs in considerable detail.
An excellent survey and tutorial on memory system design using general-purpose and special-purpose RAMs can be found in Jean-Daniel Nicoud's paper "Video RAMs: Structure and Applications," which appeared in IEEE MICRO
(February 1988), pp. 8-27. Nicoud describes how to apply video RAMs in the design of graphical frame buffers and compares the designs with those employing conventional RAMs.For a system-level perspective on interfacing hardware to memory systems, see M. Slater's textbook Microprocessor-Based Design, published by Prentice-Hall in 1989.
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