The term SOC (system-on-a-chip) has been used in the electronic industry over the last few years . However, there are still a lot of misconceptions associated with this term . A good number of practicing engineers don't really understand the differences between ASICs and SOCs. The fact that the same EDA tools are used for both ASICs and SOCs design and verification doesn't help to reduce the misconceptions.
This book describes the practical aspects of ASIC and SOC design and verification. It reflects the current issues facing ASIC/SOC designers.
The following items characterize the book:
It deals with everyday issues that ASIC/SOC designers have to face as opposed to generic textbook examples covered in other books.
It emphasizes principles and techniques as opposed to specific tools. Once the designers understand the underlying principles of practical design, they can apply them with various tools.
FPGAs will not be covered in this book. However, in Chapter 2 we cover a short section on FPGA to ASIC conversion. Earlier books have covered design and verification of FPGAs adequately.
It provides tips and guidelines for front-end and back-end designs.
Modern physical design techniques are covered.
Low-power design techniques and methodologies are explored for both ASICs and SOCs.
This book is to be used for self-study by practicing engineers. Design and verification engineers who are working with ASICs and SOCs will find the book very useful. Upper-level undergraduate and graduate students in electrical engineering can use it as a reference book in courses in logic and chip design and related topics.
The material covered in the book requires understanding of EDA tools as well as front-end and back-end processes in chip design. An initial course in logic design is required.
The book is organized in the following fashion.
In Chapter 1 we introduce the goals of this manuscript. The differences between ASICs and SOCs are introduced. The concept of Intellectual Property (IP) is covered as well as an overview of design methodologies.
SOC design challenges such as integration of IPs are also covered.
A gateway VOIP (Voice Over IP) SOC example is given in this chapter.
Chapter 2 covers an overview of ASIC design concepts, methodology, and front-end design flow. Useful guidelines for hierarchical design methodology are presented such as placement-based synthesis and interface logic models. Some key questions that ASIC designers should consider when designing ASICs are presented. FPGA to ASIC conversion is covered in Section 2.3. An overview of verification and Design for Test (DFT) techniques are also presented in this chapter.
Chapter 3 continues with the VOIP SOC example from Chapter 1. Design for integration is covered in Section 3.2. Section 3.3 covers SOC verification planning guidelines such as resource planning and regression planning. Automation and IP verification are also covered in Section 3.3. This chapter ends with a detailed design example of a Set-Top Box (STB).
Chapter 4 covers an overview of the physical design flow. Some tips and guidelines for physical design are given such as logical vs. physical hierarchy, multiple placements and routing, and non-routable congested areas.
Two examples of modern physical-design techniques are presented in Section 4.4. These methods each overcome the problems associated with traditional physical design techniques.
In Chapter 5 we present low-power design techniques. In this chapter, sources of power dissipation in CMOS devices are discussed. Several methods of power optimization at various levels of abstraction for ASICS and SOCs are explained. These techniques include: algorithm-level optimization, architecture-level optimization, RT-level optimization, and gate-level optimization. Appendix A should be used in conjunction with this chapter.
Appendix A summarizes EDA low-power design tools from Sequence Design, Inc.
Appendix B gives an overview of OCP (Open Core Protocol) that is used as a core interface standard for IP integration.
Appendix C gives an introduction to Phase-Locked Loops which are widely used in almost all ASICs and SOCs.