4.1 Review of First-Generation HDSL

   


The driving application of HDSL is to transport a DS1 payload without repeaters on loops that meet carrier serving area (CSA) requirements. CSA loops basically define a range of 9 kft on 26-gauge wire and 12 kft on 24-gauge wire. Meeting this goal would greatly simplify and cost reduce the provisioning of "high-capacity" DS1 Service to end customers. Hence, HDSL would be an alternative choice for the network operator in provisioning a DS1 access line.

Figure 4.1 shows a diagram of a DS1 access loop using repeatered T1 alternate mark inversion (AMI) technology. Conventional T1 AMI is deployed on a specially engineered repeatered line. The loop uses two wire pairs. One loop carries the full 1.544 Mb/s bit rate downstream (i.e., from the CO to the customer premises), and the other pair carries the upstream signal. Repeaters are used on the specially engineered T1 lines to reach the customer and provide the required quality of service.

Figure 4.1. Conventional repeatered T1 AMI service provisioning.

graphics/04fig01.gif

Provisioning of the repeatered lines is very labor intensive and time consuming, especially when apparatus cases for housing repeaters need to be installed. The time for provisioning the repeatered link may take up to two or three months, depending on the amount of labor needed to install all the necessary equipment.

The goal for HDSL is to deploy a circuit that transports a DS1 payload without repeaters on loops that are within CSA range. By simply identifying loops that meet CSA requirements, the provisioning time of a DS1 circuit with HDSL could be as low as two or three days. This is a significant savings and labor costs. Also note that in addition to prequalifying a loop for CSA requirements, it must be certain that the loop does not contain load coils.

The feasibility studies show that 2B1Q cannot meet the performance objective of transporting the DS1 payload to CSA range on a single wire pair in the presence of crosstalk; however, 2B1Q was observed to be robust enough to transport half the DS1 rate at CSA range in presence of self near-end crosstalk. With this observation in mind, it was agreed to define HDSL using two wire pairs to transport the DS1 payload where each wire pair transports one-half the DS1 payload in both directions (duplex). The result is the dual-duplex architecture shown in Figure 4.2.

Figure 4.2. HDSL dual-duplex provisioning of T1 service.

graphics/04fig02.gif

In the dual duplex architecture, each wire pair carries one-half of the DS1 payload along with some additional overhead for operations and maintenance reasons. The transmission on each wire pair is full-duplex transmission, where echo cancellation is the mechanism used to separate the two directions of signal transmission.

4.1.1 Dual Duplex Architecture

Figure 4.3 shows the dual-duplex architecture incorporated in first-generation HDSL. The HDSL modem is called the HDSL transceiver unit in the CO, or simply HTU-C. In the CO, the HTU-C connects to the DS1 signal via a DSX-1 interface. [1] The T1 AMI block terminates the AMI signal and converts it into a bit stream together with the recovered signal clock. The DS1 payload is then split evenly between loops #1 and #2 and the contents inserted to HDSL frames and then transmitted on their respective loops by transceiver #1 and #2. Both transceivers support duplex transmission using echo cancellation. Also, the transceivers in the HDSL pass the DS1 timing information end to end via the use of stuff and delete operations.

[1] The DSX-1 interface is a DS1 passive cross-connect defined in AT&T compatibility bulletin CB-119.

Figure 4.3. Dual-duplex architecture of HDSL.

graphics/04fig03.gif

4.1.2 DS1 Frame Structure

Figure 4.4 shows the frame structure of a DS1 payload. The basic frame structure is 125 m sec long, which is synchronized to the 8 kHz PCM sampling clock (32 ppm) in the central office. The frame is broken up into 24 time slots of 8 bits each; because each bit in the frame represents a capacity of 8 kb/s, each time slot has a capacity of 64 kb/s. The F-bit is the frame indicator bit that defines the boundary of the frame. In the 125 m sec frame period, there are 192 bits from the 24 time slots plus 1 F-bit for a total of 193 bits. This corresponds to the total bit rate of 1.544 Mb/s.

Figure 4.4. DS1 frame structure.

graphics/04fig04.gif

In addition to the core frame, the DS1 circuit is provisioned with a superframe structure that groups multiple core frames for the purpose facilitating frame boundary identification, performance monitoring, and operations and maintenance. There are two types of superframe structures defined for DS1 signals. The first is the original 12-frame superframe (SF) structure defined in AT&T Tech Pub 62411 [10], and the second is a 24-frame extended superframe (ESF) structure defined in Committee T1 Standard T1.403 [11]. The T1 AMI circuit in the HDSL modems of Figure 4.3 must first know which superframe structure the DS1 circuit is provisioned with, and it identifies the DS1 frame boundary by searching for a unique sequence of F-bits.

Once the HDSL modem synchronizes to the DS1 frame, the modem splits DS1 frame contents into two groups for transmission on the two loops. The splitting can be done in numerous ways, but the two most frequently used approaches are:

  1. Alternate the times to each pair, for example, assign the odd numbered time slots to loop #1 and the even numbered time slots to loop #2.

  2. Assign the first twelve contiguous time slots to one loop and the remainder to the other loop, for example, time slots 1 “12 are assigned to loop #1 and time slots 13 “24 are assigned to loop #2.

Having the HDSL modems know something about the DS1 circuit provisioning could enable certain service features such as passing half the DS1 payload in the unlikely event that operation on one of the HDSL loops fails. To enable such a capability, there must be consistent allocation of customer data in the DS1 frame with the splitting mechanism used in the HDSL modem.

Because HDSL transmitter locks on to the DS1 frame and splits the payload evenly between the two loops, the receiver must combine the two recovered bit streams to reconstruct the original DS1 signal. To improve the reliability in the reconstruction of the DS1 payload at the receiver, the F-bit is transmitted on both loop #1 and #2. In the event that one loop fails and the other loop remains active, the receiver must still interface to a DS1 circuit with one half of the payload. Having the F-bit transported on both loops facilitates this capability. Furthermore, an HDSL embedded operations channel (EOC) and indicator bits are also replicated on both loops.

4.2.3 HDSL Transmitter Structure

Figure 4.5 shows the transmitter structure of an HDSL system. As mentioned earlier, the T1 AMI interface circuit terminates the AMI signal and converts the AMI pulses to a bit stream and its associated clock. The splitter block divides the DS1 payload into two equal bit streams of approximately one-half the bit rate for transmission on two wire pairs in the local loop. The two bit streams are then fed to the core 2B1Q transmitters, which consist of a scrambler, bit-to-symbol mapper, and a spectral shaper. The HDSL framer and core transceiver blocks are described in the following subsections.

Figure 4.5. HDSL transmitter structure for lines #1 and #2.

graphics/04fig05.gif

4.1.4 HDSL Frame Structure

In order to reliably split the DS1 payload for transmission on two wire pairs and then reconstruct the original DS1 payload, the HDSL transceiver encapsulates the DS1 bits in an HDSL frame prior to transmission on the two wire pairs. Figure 4.6 shows a block diagram of the HDSL frame structure. In addition to identifying the specific bits and/or time slots of the DS1 payload, the HDSL frame format is constructed to support the following capabilities:

  1. Frame synchronization

  2. Performance monitoring using a 6 bit cyclic redundancy check (CRC-6)

  3. Indicator bits

  4. Embedded operations channel (EOC)

  5. Passing of DS1 timing information (rate adaptation)

Figure 4.6. HDSL frame structure.

graphics/04fig06.gif

These capabilities are supported by incorporating 8 kb/s of overhead in the frame. Both transceivers in the HDSL modem implement this frame structure. At the receiver, the frame overhead is removed prior to reconstructing the DS1 bit stream.

As seen in Figure 4.6, the HDSL frame structure contains a superframe that is 6 msec. This period corresponds to 48 DS1 core frame periods. For every DS1 core frame included in the HDSL superframe, we include one additional bit of overhead, which corresponds to including 8 kb/s or over in the HDSL line signal. Hence, each HDSL superframe contains 48 overhead bits and the appropriate data from 48 DS1 core frames.

The frame is broken up into the following components of overhead and payload:

  1. Four payload blocks, labeled PB1 “PB4, in which is placed the DS1 data assigned to the specific line

  2. Four overhead blocks labeled OH1 “OH4

  3. Stuff bits (2 stuff bits constitute a nominal frame) labeled SB

Each payload block contains 12 sub-blocks of DS1 data. As seen in the figure, each sub-block contains one DS1 F-bit and 12 time slots from the DS1 payload. In this example, we assign the odd numbered time slots to the HDSL frame of loop #1 and the even numbered slots to the frame in loop #2. The same DS1 F-bit is transported on both lines. There are graphics/04inl05.gif in each payload block, so the entire superframe contains 4,656 payload bits. If we add the 48 overhead bits, we get 4,704 total bits in each 6 msec superframe, which corresponds to a bit rate of 784 kb/s that is transmitted on each wire pair.

The first overhead block contains 14 bits that are dedicated for frame identification and synchronization. The frame sync word (FSW) is a double (or interleaved) Barker code defined as 11111100001100. Using the 2B1Q line code, this FSW sequence is transmitted with the outermost 2B1Q symbols, namely, sequence +3 +3 +3 -3 -3 +3 -3. Barker codes have superior autocorrelation properties and are effective in timely synchronization of the HDSL frame. Note that dibit 11 is mapped to 2B1Q symbol +3 and dibit 00 is mapped to 2B1Q symbol -3. The downstream direction of transmission uses the above-mentioned FSW; the upstream direction uses the reverse FSW sequence, namely, -3 +3 -3 -3 +3 +3 +3.

Overhead blocks OH2 “OH4 each have 10 bits. Six bits are allocated for transport of a CRC output for the purposes of performance monitoring. The remaining bits are allocated for indicator bits and an EOC. The assignment of 24 bits to an EOC provides a capacity of 4 kb/s for data communication. There have been different assignments of these in various HDSL systems; G.991.1 provides definitions for HDSL systems in Europe and in North America.

The stuff bits at the end of the superframe provide the mechanism for transferring DS1 signal timing information end to end. If the HDSL frame buffer is approaching overflow because the HDSL line clock is not reading the buffer data fast enough, then the framer would eliminate transmission of the stuff bits at the end of the current frame. Alternatively, if the HDSL frame buffer is approaching empty because the HDSL line clock is reading the data too fast, then the framer would insert four stuff bits into the current frame to allow more payload bits to be loaded into the buffer.

The stuff and delete operations for the 2B1Q systems defined in G.991.1 transmit either 0 or 4 stuff bits; the nominal frame of 6 msec is never sent, it is only seen on the average transmission of many superframes. In the CAP-based systems defined in G.991.1, the framer may include 0, 2, or 4 stuff bits; in these systems, the nominal superframe of 6 msec is often sent. Having the finer stuffing resolution allows for better timing jitter performance.

4.1.5 Scrambler

The HDSL transceivers use a self-synchronizing scrambler to randomize the data for transmission on the line. All of the bits except for the 14-bit frame sync word and the stuff bits are scrambled. In all cases the scramblers use a 23rd order polynomial. In the downstream direction, the scrambler polynomial is p ( x ) = 1 + x -5 + x -23 and that for the upstream channel is p ( x ) = 1 + x -5 + x -23 , where the + sign indicates modulo-2 addition. Figure 4.7 shows the block diagrams of the downstream and upstream channel scramblers and descramblers. Note that these are the same scramblers and descramblers used in basic rate ISDN [3].

Figure 4.7. Downstream and upstream channel scramblers and descramblers.

graphics/04fig07.gif

4.1.6 Bit-to-Symbol Mapping

The bit-to-symbol map block converts the serial bit stream into a sequence of multilevel pulses. For 2B1Q, the mapping block takes two bits at the input and produces a sequence of pulses that contain four possible levels. Figure 4.8 shows an example 2B1Q bit mapping taken from ETSI TS 101 135 [7]. In this example, the first bit defines the sign of the output pulse where a one maps to a positive ampli tude pulse and a zero maps into a negative amplitude pulse. The second bit defines the magnitude of the output pulse where a one maps to the lower pulse amplitude and the zero maps to the larger pulse amplitude.

Figure 4.8. Bit-to-symbol mapping in 2B1Q HDSL.

graphics/04fig08.gif

The input bit sequence has a bit rate of R b bits/sec; the corresponding bit interval is T b = 1/ R b seconds. Since the mapping block collects two bits for each multi-level symbol, the output symbol interval is twice the bit interval; hence the symbol rate is R S = 1/2 T b = R b /2. For 2B1Q, the output symbol rate is one half that of the input bit rate.

For two-pair HDSL in North America [4],[9] and three-pair HDSL in Europe [7],[9], the bit rate on each wire pair is 784 kb/s, and the corresponding symbol rate is 392 kBaud (kSymbols/s). The 3-dB signal bandwidth is 196 kHz.

For two-pair HDSL in Europe transporting a 2.048 Mb/s E1 payload, the line bit rate is 1,168 kb/s on each wire pair, and the corresponding symbol rate is 584 kBaud. The 3-dB signal bandwidth is 292 kHz.

4.1.7 2B1Q Spectral Shaper

The spectral shaper is a low pass filter that shapes the transmit signal spectrum to a form suitable for transmission in loop plant. The 2B1Q transceiver uses a simple spectral shaper, that is, one that provides a fourth order roll-off. The fourth order roll-off is defined via a PSD mask in Section 5.8.4 of the ETSI technical specification on HDSL [7]. Typical implementation of HDSL systems pass a 2B1Q NRZ (non-return to zero) spectrum through a fourth-order Butterworth filter and scale that signal such that the total transmit power is 13.5 dBm.

The HDSL transmit signal power spectral density (PSD) can be mathematically modeled by the following equation:

graphics/04equ01.gif


where f = 392 kHz, f 3 dB = 196 kHz, graphics/04inl02.gif , V p = 270 Volts, and R = 135 .

The above PSD expression models the passing of a rectangular pulse through a fourth order Butterworth filter. The magnitude of the expression is scaled to produce a transmit signal power of 13.5 dBm. Figure 4.9 shows a plot of a nominal HDSL transmit PSD scaled to have a 13.5 dBm transmit power in the interval from 0 to 392 kHz.

Figure 4.9. Nominal 2B1Q HDSL transmit PSD (784 kb/s) with 4th-order roll-off.

graphics/04fig09.jpg

Note that for frequencies above the first null at f = 392 kHz, there is still significant energy in the image lobes . This out-of- band energy is important when considering the crosstalk into other systems. Note that crosstalk coupling to other wire pairs in a cable increases with increasing frequency. A shaping filter with a higher roll-off could further reduce this out-of-band energy, which would reduce the amount of crosstalk into other signals deployed in the cable.

4.1.8 2B1Q HDSL Transceiver Structure

There are numerous ways to build a 2B1Q transceiver. Figure 4.10 shows a functional block diagram of an HDSL transceiver supporting the 2B1Q line code. The blocks shown are those that implement the core modem. The top row of blocks implement the transmitter, and the bottom row of blocks implement the receiver function. Because the upstream and downstream channels share the same frequency band, the duplexing function is provided with echo cancellation.

Figure 4.10. Functional block diagram of a 2B1Q HDSL transceiver.

graphics/04fig10.gif

As discussed earlier, the transmitter of the core modem consists of the scrambler [2] , bit-to-symbol mapping, spectral shaping filter, and an analog front end that includes a line driver. The scrambler feeds the bit-to-symbol mapping block that converts the serial bit stream to a sequence of four level pulses as shown in the example of Figure 4.8. The spectral shaper filters the multilevel pulse stream for the bit-to-symbol map block to a spectral shape suitable for transmission on the line. The filter may be implemented with either analog or digital processing. If analog processing is used, then the filtered signal may be fed directly to the line driver. If the filtering is done with digital processing, then the digital-to-analog (D/A) converter converts the digital samples into analog samples, which are then fed to the line driver for transmission on the subscriber line.

[2] The scrambler and descrambler blocks are not shown in the figure; however, the scrambler connects to transmitter input and the receiver output (symbol-to-bit mapper) connects to the descrambler input.

The hybrid circuit provides the four-to-two wire coupling of the transceiver to the subscriber line. Both the transmitter output and receiver input have two-wire connections to the hybrid circuit. The subscriber line is a single wire pair that transports signals in both directions. A balancing circuit (not shown in the figure) minimizes the leakage of the transmitter output signal into the local receiver input. An ideal hybrid would have no leakage of the local transmit signal into the local receiver, that is, infinite trans-hybrid loss; however, practical hybrids would have around 12 dB of trans-hybrid loss. This amount of trans-hybrid loss allows a significant amount of energy from the local transmitter that must be compensated for in the receiver.

Given that the hybrid circuit is far from an ideal device, the level of the signal leaking from the local transmitter into the local receiver, hereby referred to as the local echo, is typically higher than the level of the desired signal from the far-end transmitter. It is the job of the echo canceler to remove this local echo seen at the receiver input so that information in the desired received signal may be recovered with a high degree of confidence.

For example, let's assume that the subscriber loop attenuates the far-end transmit signal by about 40 dB and the local hybrid circuit has 12 dB of trans-hybrid. Assuming that the transmit signals at both ends of the line each have the same transmit power, then the level of the local echo will be 28 dB higher than the level of the local echo. If for reliable decoding of the desired received signal we desire the level local echo to be 30 dB below the desired received signal, then the echo canceler will need to provide at least 58 dB (28 dB + 30 dB) of echo cancellation. Good echo canceler designs typically provide at least 60 dB of echo cancellation.

As mentioned earlier, the input to the receiver includes the desired receive signal sent from the far-end transmitter across the subscriber line and a local echo resulting from leakage through the hybrid. The receiver first filters the received signal to remove any unwanted out-of-band noise and automatically adjusts the level of the total received signal, using either an automatic gain control (AGC) circuit or a programmable gain amplifier (PGA), for optimum use of the analog to digital (A/D) converter's dynamic range. Additional digital filtering may then be done on the digitized samples of the received signal.

Prior to recovering the desired signal, the local echo must be removed from the total received filtered signal. At initialization, the echo canceller circuit automatically learns the echo path between the near-end transmitter and near-end receiver. The echo path is that through the shaping filter, transmitter's analog front end, hybrid circuit, the receiver's filters and A/D converter. The reconstructed echo signal is subtracted from the filtered total receive signal. The receiver then uses a conventional decision feedback equalizer to compensate for the channel impairments, namely loop attenuation and phase distortion, crosstalk, residual echo, and background noise. Finally, the symbol-to-bit mapping block converts the 2B1Q samples to bits, which are then sent to the descrambler.

4.1.9 CAP-Based HDSL

As shown in Chapter 2, for any given baseband system it is always possible to design an equivalent passband system. By equivalent systems we mean that the two systems have the same bit rate, the same transmit power, and they both utilize the same bandwidth. If we consider a reference four-level PAM (pulse amplitude modulation) system as an example, a corresponding equivalent passband system may be implemented using 16-level CAP (carrierless amplitude and phase modulation) or QAM (quadrature amplitude modulation) as shown in Figure 4.11.

Figure 4.11. Example equivalent baseband and passband systems.

graphics/04fig11.jpg

A baseband PAM has a one-dimensional constellation. The minimum required bandwidth is one-half the symbol rate, which is shown in the spectrum diagram Figure 4.11(a) as R S /2, where R S is the symbol rate of the PAM system. If a single carrier of frequency f c modulated the baseband spectrum, then the bandwidth of the resulting passband spectrum would be doubled . To obtain an equivalent bandwidth as the baseband system, the passband symbol rate would need to be halved. This is achieved by taking the original bit stream and converting it into two parallel symbol sequences, each running at one-half the baseband symbol rate; the two parallel symbol sequences may be modulated with quadrature carriers and added together to form a passband transmit signal having the same equivalent bandwidth as the corresponding baseband system. The differences are that the passband system has a two-dimensional constellation that is square the size and twice as many bits per symbol as the reference baseband system and the symbol rate of the passband system is half that of the reference baseband system. The bit rate and bandwidth are equivalent and both spectra may be scaled to produce the same transmit power.

In general, a baseband PAM system will have the following parameters:

  • Bit rate R B

  • Symbol rate : R S = R B / b

  • One-dimensional constellation with N = 2 b levels

  • b bits per baseband symbol

  • Minimum bandwidth of R S /2

The corresponding equivalent passband PAM (i.e., using CAP or QAM) system will have the following parameters

  • Bit rate R B

  • Symbol rate : R S ' = R S /2 = R B /2 b

  • Two-dimensional constellation with N ' = N 2 = 2 2b levels

  • 2 b bit per passband symbol

  • Minimum bandwidth of R S ' = R S /2.

The functional block diagram of a CAP based transceiver is shown in Figure 4.12. There are two fundamental differences in this structure compared with the 2B1Q functional block diagram of Figure 4.10. Because CAP is a passband system, the symbol processing is done in two dimensions; in the figure, double lines connecting the functional blocks represent the passing of two-dimensional symbols. Second, the CAP transceiver uses a trellis code to provide added immunity to crosstalk. A channel precoder is used together with the trellis encoder so that the transceiver can achieve the joint benefits of the trellis code and a decision feedback equalizer.

Figure 4.12. CAP-based HDSL transceiver functional block diagram.

graphics/04fig12.gif

The trellis code chosen for the CAP system is based on the two-dimensional eight-state (2D8S) code [40] that is used in V.32 modems [15]. This provides an asymptotic code gain of approximately 4 dB. This additional coding gain adds roughly a 1-kft reach improvement on 26-gauge wire over 2B1Q systems.

The rate of the trellis code is n/(n+1), where for each n input information bits, the trellis code outputs one additional bit for redundancy. Hence, the CAP transmitter will transmit a constellation base on n + 1 bits. When compared with the 2B1Q transceiver, the equivalent uncoded CAP system has sixteen points in the constellation. When we add the 2D8S trellis code, the equivalent CAP system contains thirty-two levels.

The actual CAP system defined in Annex B of the ETSI HDSL technical specification [7] uses a sixty-four-point coded constellation. The spectral shaping is that of a square-root raised-cosine spectrum with at least 30 dB out of band rejection . Although the coded thirty-two-point constellation gives optimum performance against the worst-case self-NEXT crosstalk, the operation of coded 64-point CAP has less than a 0.5 dB degradation. However, the narrower bandwidth and efficient spectral shaping provides significantly less crosstalk into other systems in the cable. Of particular interest is the spectral compatibility with ADSL. The narrower bandwidth of coded 64-CAP and the low out-of-band energy provides significantly better spectral compatibility with ADSL than does the 2B1Q HDSL.


   
Top


DSL Advances
DSL Advances
ISBN: 0130938106
EAN: 2147483647
Year: 2002
Pages: 154

flylib.com © 2008-2017.
If you may any questions please contact us: flylib@qtcs.net