2.4. OPTIMIZING COMPILERS

2.3. PROGRAMMING MODEL

Vector and superscalar architectures are united in a single group for a number of reasons. One is that the most successful vector architectures are very close to superscalar architectures both ideologically and in implementation. Indeed, the vector pipelined unit presented above can be seen as a specialized clone of the general-purpose superscalar pipelined unit, which is optimized for pipelined execution of n successive instructions performed as the same operation but on different operands. The optimization is that due to its specialization the vector pipelined unit does not need a decoding stage and therefore uses a more effective data pipeline instead of the instruction pipeline. On the other hand, the design of some advanced superscalar processors, such as Intel i860, is obviously influenced by the vector-pipelined architecture.

But the most important reason is that these architectures share the same programming model. Namely a good portable program that can take full advantage of the performance potential of superscalar processors is defined in the same way as for vector processors. Indeed, what makes this a good program for vector processors? It is the program’s use of a wide range of vector instructions that implement basic operations on arrays. Like wise a program intensively using basic operations on arrays is perfectly suitable for superscalar processors in that it allows a very high level of utilization of their pipelined units.

Of course, unlike vector processors, superscalar processors allow more sophisticated mixtures of operations to efficiently load their pipelined units than just basic array operations. But normally such mixtures are rather specific for each superscalar processor and therefore are not portable. Second, most of the mixtures are quite esoteric and rarely relevant in real-life applications. Last, even in the odd case where a real-life application is potentially able to load the pipelined units of the superscalar processor with some complex mixture of operations, the problem of writing/generating the corresponding efficient code may seem too difficult to justify undertaking its solution. Therefore, even if the superscalar architecture looks richer than the vector architecture, the real programming model used for superscalar processors should be the same as the programming model for vector processors.