| Instructions in the makefile are interpreted as single lines. If an instruction must span more than one input line, use a backslash (\) at the end of the line so that the next line is considered a continuation. The makefile may contain any of the following types of lines:
Blank lines Blank lines are ignored.
Comment lines A number sign (#) can be used at the beginning of a line or anywhere in the middle. make ignores everything after the #.
Dependency lines One or more target names, a single- or double-colon separator, and zero or more prerequisites: targets : prerequisites targets :: prerequisites
In the first form, subsequent commands are executed if the prerequisites are newer than the target. The second form is a variant that lets you specify the same targets on more than one dependency line. (This second form is useful when the way you rebuild the target depends upon which prerequisite is newer.) In both forms, if no prerequisites are supplied, subsequent commands are always executed (whenever any of the targets are specified). For example, the following is invalid, since single-colon rules do not allow targets to repeated: # PROBLEM: Single colon rules disallow repeating targets whizprog.o: foo.h $(CC) -c $(CFLAGS) whizprog.o @echo built for foo.h whizprog.o: bar.h $(CC) -c $(CFLAGS) whizprog.o @echo built for bar.h
In such a case, the last set of rules is used and make issues a diagnostic. However, double-colon rules treat the dependencies separately, running each set of rules if the target is out of date with respect to the individual dependencies: # OK: Double colon rules work independently of each other whizprog.o:: foo.h $(CC) -c $(CFLAGS) whizprog.o @echo built for foo.h whizprog.o:: bar.h $(CC) -c $(CFLAGS) whizprog.o @echo built for bar.h
No tab should precede any targets. (At the end of a dependency line, you can specify a command, preceded by a semicolon; however, commands are typically entered on their own lines, preceded by a tab.) Targets of the form library(member) represent members of archive libraries, e.g., libguide.a(dontpanic.o). Furthermore, both targets and prerequisites may contain shell-style wildcards (e.g., *.c). make expands the wildcard and uses the resulting list for the targets or prerequisites.
Suffix rules These specify that files ending with the first suffix can be prerequisites for files ending with the second suffix (assuming the root filenames are the same). Either of these formats can be used: .suffix.suffix: .suffix:
The second form means that the root filename depends on the filename with the corresponding suffix.
Pattern rules Rules that use the % character define a pattern for matching targets and prerequisites. This is a powerful generalization of the original make's suffix rules. Many of GNU make's built-in rules are pattern rules. For example, this built-in rule is used to compile C programs into relocatable object files: %.o : %.c $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@
Each target listed in a pattern rule must contain only one % character. To match these rules, files must have at least one character in their names to match the %; a file named just .o would not match the above rule. The text that matches the % is called the stem, and the stem's value is substituted for the % in the prerequisite. (Thus, for example, prog.c becomes the prerequisite for prog.o.)
Conditional statements Statements that evaluate conditions, and depending upon the result, include or exclude other statements from the contents of the makefile. More detail is given in the section "Conditional Input," later in this chapter.
Macro definitions Macro definitions define variables: identifiers associated with blocks of text. Variable values can be created with either =, :=, or define, and appended to with +=. More detail is provided in the later section "Creating and Using Macros."
include statements Similar to the C #include directive, there are three forms: include file [file ...] -include file [file ...] sinclude file [file ...]
make processes the value of file for macro expansions before attempting to open the file. Furthermore, each file may be a shell-style wildcard pattern, in which case make expands it to produce a list of files to read. The second and third forms have the same meaning. They indicate that make should try to include the named lines, but should continue without an error if a file could not be included. The sinclude version provides compatibility with other versions of make.
vpath statements Similar to the VPATH variable, the vpath line has one of the following three forms: vpath pattern directory ... Set directory list for pattern vpath pattern Clear list for pattern vpath Clear all lists
Each pattern is similar to those for pattern rules, using % as a wildcard character. When attempting to find a prerequisite, make looks for a vpath rule that matches the prerequisite, and then searches in the directory list (separated by spaces or colons) for a matching file. Directories provided with vpath directives are searched before those provided by the VPATH variable.
Command lines These lines are where you give the commands to actually rebuild those files that are out of date. Commands are grouped below the dependency line and are typed on lines that begin with a tab. If a command is preceded by a hyphen (-), make ignores any error returned. If a command is preceded by an at sign (@), the command line won't echo on the display (unless make is called with -n). Lines beginning with a plus (+) are always executed, even if -n, -q, or -t are used. This also applies to lines containing $(MAKE) or ${MAKE}. Further advice on command lines is given later in this chapter.
16.3.1. Special Dependencies GNU make has two special features for working with dependencies.
Library dependencies A dependency of the form -lNAME causes make to search for a library file whose name is either libNAME.so or libNAME.a in the standard library directories. This is customizable with the .LIBPATTERNS variable; see the later section "Macros with Special Handling" for more information.
Order-only prerequisites When a normal prerequisite of a target is out of date, two things happen. First, the prerequisite (and its prerequisites, recursively) are rebuilt as needed. This imposes an ordering on the building of targets and prerequisites. Second, after the prerequisites are updated, the target itself is rebuilt using the accompanying commands. Normally, both of these are what's desired. Sometimes, you just wish to impose an ordering, such that the prerequisites are themselves updated, but the target is not rebuilt by running its rules. Such order-only prerequisites are specified in a dependency line by placing them to the right of a vertical bar or pipe symbol, |: target: normal-dep1 normal-dep2 | order-dep1 order-dep2 command
Dependency lines need not contain both. I.e., you do not have to provide regular dependencies if there are order-only dependencies as well; just place the | right after the colon.
Here is an annotated example of an order-only dependency: $ cat Makefile all: target First target is default, point to real target prereq0: How to make prereq0 @echo making prereq0 touch prereq0 prereq1: How to make prereq1 @echo making prereq1 touch prereq1 prereq2: prereq0 prereq2 depends on prereq0 @echo making prereq2 touch prereq2 target: prereq1 | prereq2 How to make target @echo making target touch target
The order of creation is shown in Figure 16-1. Figure 16-1. The order of creation 
And here is the result of running make: $ make making prereq1 touch prereq1 making prereq0 touch prereq0 making prereq2 touch prereq2 making target touch target
This is normal and as expected. Now, let's update one of the order-only prerequisites and rerun make: $ touch prereq0 $ make making prereq2 touch prereq2
Note that target was not rebuilt! Had the dependency on prereq2 been a regular dependency, then target itself would also have been remade. 16.3.2. Conditional Input Conditional statements allow you to include or exclude specific lines based on some condition. The condition can be that a macro is or is not defined, or that the value of a macro is or is not equal to a particular string. The equivalence/nonequivalence tests provide three different ways of quoting the values. Conditionals may have an optional "else" part; i.e., lines that are used when the condition is not true. The general form is as follows: ifXXX test lines to include if true [ else lines to include if false ] endif
(The square brackets indicate optional parts of the construct; they are not to be entered literally.) Actual tests are as follows: Condition | Meaning |
|---|
ifdef macroname | True if macroname is a macro that has been given a value. | ifndef macroname | True if macroname is a macro that has not been given a value. | ifeq (v1,v2) | | ifeq 'v1' 'v2' | True if values v1 and v2 are equal. | ifeq "v1" "v2" | | ifneq (v1,v2) | | ifneq 'v1' 'v2' | True if values v1 and v2 are not equal. | ifneq "v1" "v2" | |
For example: whizprog.o: whizprog.c ifeq($(ARCH),ENIAC) # Serious retrocomputing in progess! $(CC) $(CFLAGS) $(ENIACFLAGS) -c $< -o $@ else $(CC) $(CFLAGS) -c $< -o $@ endif
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