2.5 Summary
2.5 Summary
Table 2.1 compared complexity, speed, cost, and available I/Os for gate arrays and standard-
The major factors involved in a design TAT are frequency of operation, number of gates, density, number of clock domains, and number of blocks and sub-blocks.
The basic front-end design flow was discussed in Section 2.2. Hierarchical methodology, the use of placement-based synthesis, and the use of ILM models are recommended for designs bigger than two million gates.
FPGA to ASIC conversion was discussed in Section 2.3. Some benefits of the conversion include:
-
Die
size reduction -
Power consumption reduction
-
Enhanced performance
-
Reliable high-volume production capacity
-
Low NRE
An overview of the verification techniques and DFT was discussed in Section 2.4. We will cover more on verification issues in Chapter 3.
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2.6 References
1. J. Bergeron. Writing Testbenches . Norwell, MA: Kluwer Academic Publishers, 2000.
2. www.cis.ohiostate.edu/~harrold/research/regression_testing.htm
3. M. J. S. Smith. Application-Specific Integrated Circuits . Reading, MA: Addison-Wesley, 1997.
4. D. Hsu. "DFT Closure in SOC Design." Synopsys, Inc., Mountain View, CA, 2000.
5. J. Desposito. "SOC and Deep-Submicron Technology Drive New DFT Strategies." Electronic Design, 1998.
6. "JTAG Boundary Scan Testing." Testability Primer, Texas Instruments, 1997.
7. B. Murray and J. Hayes. "Testing IC's: Getting to the Core of the Problem," Computer , Vol. 29, No. 11, IEEE, November 1996.
8. A. Crouch. Design for Test . Upper Saddle River, NJ: Prentice Hall, 1999.
9. "Solving the Challenges of Testing Small Embedded Cores and Memories Using FastScan Macro Test." Mentor Graphics, 2000.
10. M. Keating and P. Bricaud. Reuse Methodology Manual for System-on-a-Chip Designs . Norwell, MA: Kluwer Academic Publishers, 1999.
11. F. Nekoogar. Timing Verification of Application Specific Circuits (ASICs) . Upper Saddle River, NJ: Prentice Hall PTR, 1999.
12. Spring Tech Seminars, Verification 2001, Synopsys, Inc., Mountain View, CA.
13. ASIC Products Application Notes. "Application of Synopsys Physical Compiler in IBM ASIC Methodology." IBM, August 2001.
14. ASIC Products Application Notes. "Application of Cadence Envisia PKS in IBM ASIC Methodology." IBM, May 2001.
15. CMOS ASIC CS81/CE81 Series, Product information notes. Fujitsu, March 2000.
16. "FPGA to ASIC Conversion Program." Epson Electronics America, Inc., November 2000.
17. www.amis.com/conversion
18. "Hierarchical Static Timing Analysis Using Interface Logic Models, PrimeTime." Synopsys, Inc., Mountain View, CA, January 2001.
19. "Best Practices and Advanced Verification Techniques." Spring Tech Seminars, Verification 2001, Synopsys, Inc., Mountain View, CA.
20. "Complete Best-in-Class Synthesis Solution." Spring Tech Seminars, Synthesis 2001, Synopsis, Inc., Mountain View, CA.
21. www.cadence.com/
22. www.cadence.com/products/fv.html
23. N. Deo. "Tools and Technologies for Deep Submicron IC Design." 1997.
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Chapter 3. SOC Design and Verification
Section 3.1. Introduction
Section 3.2. Design for Integration
Section 3.3. SOC Verification
Section 3.4. Set-Top-Box SOC
Section 3.5. Set-Top-Box SOC Example
Section 3.6. Summary
Section 3.7. References
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