Answer the first four questions with DRAM, SRAM, or both.
Which technology uses capacitors to store data?
Which technology is faster?
Which technology is used in cache?
Which technology stores data in a grid?
What innovation did DDR RAM introduce?
Transfers data on both the rising and falling edge of each clock cycle
Distributes data across DIMMs in two banks
Adds a parity bit to each byte when it writes it to memory
Corrects single-bit errors
Which memory technology doubles the amount of data obtained in a single memory access from 64 bits to 128 bits?
DDR RAM
Online spare memory
Hot-plug RAID memory
Interleaved memory
Match the fault-tolerant technology with its description:
Parity
This technology uses a checksum to analyze an error, determine which byte is corrupt, and correct it.
ECC
Four memory controllers each write one block of data to one of four DIMMs. A fifth memory controller stores parity information on a fifth DIMM.
Advanced ECC
A memory bank with a faulty DIMM automatically fails over to a spare bank of DIMMs.
The memory controller writes the same data to identically configured banks of DIMMs on two memory boards.
Hot-plug mirrored memory
The memory controller adds a bit to each byte when it writes the byte to memory based on the number of 1s in the byte.
This technology corrects multibit errors that occur on a single DRAM chip.
What is the benefit of cache in a server?
Fills data requests from the processor more quickly than memory
Doubles the amount of data that can be stored on the hard drive
Decodes instructions to make the processor work faster
Increases the clock speed of the memory bus
Which cache stores the first data checked by the processor?
Which bus connects the L2 cache to the processor?
Frontside bus
Backside bus
System bus
PCI bus
What is the function of the tag RAM?
Match the cache implementation to its definition:
Look-aside
A cache controller listens in to system bus traffic for any memory requests made by bus masters.
Look-through
When a bus master is trying to write to memory, the cache controller captures the data being written and writes it to cache.
Fully associated
A bit attached to the cache line is flagged to indicate that the data has not yet been written to memory.
Direct mapped
Data from main memory can be stored in any cache line.
Set-associative
The system must write the data through all the memory levels before it can be used again.
Write-through
Both cache and memory receive memory requests. If there is a cache hit, the cache controller terminates the request to the other devices.
Write-back
A group of memory addresses is assigned to each cache line.
Bus snooping
If there is a cache hit, no request makes it to the system bus.
Bus snarfing
A group of memory addresses is assigned to a specific group of cache lines.