1-1 Typical PCI North-South Bridge System
1-2 Sample HT-based System
2-1 Example HyperTransport System
2-2 HT Address Map
2-3 Transaction Flow During Programmed I/O Operation
2-4 Transaction Flow During DMA Operation
2-5 Peer-to-Peer Transaction Flow
2-6 Primary HT Signal Groups
2-7 Link Signals Used to Transfer Packets
2-8 Link Support Signals
2-9 Scalable Link Width and Speeds
2-10 Link Widths Supported
2-11 Basic HT Device Types
2-12 HyperTransport Topology Supporting All Three Major Device Types
2-13 Distinguishing Control from Data Packets
2-14 HT Virtual Channels
2-15 Example Protocol ” Receiving Data from Target
2-16 Example Protocol ” Non-Posted Sized Write
2-17 Example Protocol ” Posted Sized Write
2-18 Example Protocol ” Flush Transaction
2-19 Example Protocol ” Fence Transaction
2-20 Example Protocol ” Atomic Operation
2-21 Example of Packet Flow During Broadcast Transaction
3-1 HyperTransport Signal Groups
4-1 Four Byte Packet On An 8-Bit Interface
4-2 Four Byte Packet On A 2-Bit Interface
4-3 Four Byte Packet On A 16-Bit Interface
4-4 Four Byte Packet On A 32-Bit Interface
4-5 CAD Bus Control/Data Packet Management Using the CTL Signal
4-6 Control Packets: NOP Information
4-7 Control Packets: Sync Information
4-8 Control Packets: Generic Sized Read/Sized Write Requests
4-9 Control Packets: Broadcast Message Request
4-10 Control Packets: Flush Request
4-11 Control Packets: Fence Request
4-12 Control Packets: Atomic Read-Modify-Write Request
4-13 Control Packets: Read Response
4-14 Control Packets: Target Done Response
5-1 PCI Interface Handshake Signals
5-2 Flow Control Is On A Link-By-Link Basis
5-3 Flow Control Buffers And Counters
5-4 Flow Control Counter Initialization
5-5 Device 1 Sends Two Packets
5-6 Device 2 Updates Flow Control Information
6-1 PIO, DMA, And Peer-to-Peer Traffic
6-2 Targets At Different Levels In Hierarchy And In Different Chains
6-3 Non-Posted Requests And Responses At Target
6-4 Upstream Reordering: Packets From Different Transaction Streams
6-5 A Strongly Ordered Sequence Must Be Preserved
6-6 Packets With PassPW Clear Can't Pass Posted Requests
6-7 Packets With PassPW Set May Or May Not Pass Other Posted Requests
6-8 Non-Posted Requests May Pass Each Other
6-9 Posted Request Or Response Must Be Able To Pass Non-Posted Requests
6-10 Posted Request Must Be Able To Pass An Earlier Response
6-11 Non-Posted Request/Response May Pass Earlier Responses
6-12 Host Bridge Extends Ordering To Host System
6-13 Ordering Example: Read Followed By Posted Write To Cacheable Memory
6-14 Double-Hosted Chain Ordering
7-1 Example 1: NOP Information Packet With Buffer Updates
7-2 Generic RdSized And WrSized Request Packet Format
7-3 Generic Read/Target Done Response Packet Format
7-4 DMA Non-Posted Write Targeting Main Memory
7-5 Posted WrSized (Byte) Write Targeting A Downstream Device
7-6 DMA Dword Read Targeting Main Memory
7-7 DMA Byte Read Targeting Main Memory
7-8 A Flush Request Issued By UnitID 2
7-9 A Fence Request Issued By UnitID 3
7-10 Atomic Read-Modify-Write Targeting Main Memory
7-11 Sized (Dword) Write Transaction Must Cross A Bridge
8-1 Interrupt Capability Block Indicates that the Device Supports Interrupts
8-2 Interrupt Request and EOI Message Reserved Address Range
8-3 Interrupt Request Packet Address Field
8-4 Format of Interrupt Request Packet
8-5 Format of the Interrupt Request Data Packet
8-6 EOI Packet Format
8-7 Format of Interrupt Discovery and Configuration Capability Block
9-1 SM Request Sources
9-2 Format of SM Request Packet Issued by the System Management Controller
9-3 Format of SM Request Packet Issued by the Host Bridge
9-4 Theoretical System with LDTSTOP# Support
10-1 8/16/32 Bit Interfaces: CRC Inserted Into CAD Stream Every 512 Bit Times
10-2 Link Control CSR: CRC Error Logging Bits
10-3 Error Handling CSR: CRC Error Interrupt Enables
10-4 Link Control Register: CRC Sync Flood Enable bit
10-5 Link Error Register: Protocol Error Logging Bits
10-6 Error Handling CSR: Protocol Error Reporting Enables
10-7 Link Error Register: Receive Buffer Overflow Error Logging Bits
10-8 Error Handling CSR: Receive Buffer Overflow Error Reporting Enables
10-9 End-Of-Chain Device Determination
10-10 Link Error Register: End-Of-Chain Error Logging Bits
10-11 Error Handling CSR: End-Of-Chain Error Reporting Enables
10-12 Error Handling Register: Chain Fail Bit
10-13 Error Handling CSR: Response Error Logging And Reporting Policy Bits
10-14 Response Packet And Error Bits
10-15 Sync Flood Example
11-1 Routing: Shared Bus vs. HyperTransport Point-Point
11-2 Generic WrSized Or RdSized Request Packet: Key Routing Fields
11-3 Generic Read/Target Done Response Packet: Key Routing Fields
11-4 Tunnel Inserting Packets Into Upstream Traffic
12-1 Example of Reset Distribution in an HT System
12-2 Example HT-to-HT Bridge Forwarding Cold Reset
12-3 Bridge Control Register Can Force Cold Reset
12-4 Cold Reset Signalling
12-5 RESET# and PWROK Sequence and Timing Requirements
12-6 Low-Level Link Width, Example 1
12-7 Low-Level Link Width, Example 2
12-8 Low-Level Link Width, Example 3
12-9 Link Configuration Register
12-10 Link Interface and Clocking
12-11 Clock Synchronization and FIFO Load and Unload Pointer Setup
12-12 Duration of CTL & CAD Deassertion
12-13 Framing and CRC Window Sequence
12-14 Link Width Update
12-15 Maximum Link Values, Example 1
12-16 Maximum Link Values, Example 2
12-17 Maximum Link Values, Example 3
12-18 Tunnel Example ” Link Frequency Capability Registers
12-19 Link Frequency Register Location within the HT Capability Register Set
12-20 HyperTransport Host Command CSR
13-1 PCI Type 1 and Type 0 Configuration Cycles
13-2 Configuration Space In The HyperTransport Address Map
13-3 Configuration Type 0 And Type 1 Request Packet Format
13-4 HyperTransport Type 1 And Type 0 Configuration Cycles
13-5 Bus Numbering In A Mixed Topology
13-6 Bus Numbering In Double-Hosted Chains
13-7 PCI Type 0 Configuration Space Header
13-8 PCI Configuration Space With Advanced Capability Register Block(s)
13-9 HyperTransport Technology Header Command Register Usage
13-10 HyperTransport Technology Header Status Register Usage
13-11 HyperTransport Advanced Capability Block Types
13-12 Slave/Primary Interface For Tunnel And Cave Devices
13-13 Slave/Primary Interface Block Format
13-14 HyperTransport Slave Command CSR
13-15 Slave Interface Block Link Control Registers 0,1
13-16 Slave Interface Link Configuration Registers 0,1
13-17 Slave Interface Revision ID Register
13-18 Slave Interface Link Frequency Registers 0,1
13-19 Slave Interface Link Error Registers 0,1
13-20 Slave Interface Link Frequency Capability Registers 0,1
13-21 Slave Interface Feature Capability Register
13-22 Slave Interface Enumeration Scratch Pad Register
13-23 Slave Interface Error Handling Register
13-24 Slave Interface Memory Base/Limit Upper Registers
13-25 Host/Secondary Interface For Bridge Devices
13-26 Host/Secondary Command Register Format.
13-27 HyperTransport Host Command CSR
13-28 Host Interface Feature Capability Register
13-29 Revision ID Capability Block
14-1 Link Signals
14-2 HT Link Differential Driver and Receiver
14-3 DC Impedance Values
14-4 DC Output Voltage Measurements
14-5 Differential DC Input Voltage Parameters
14-6 AC Impedance Values
14-7 Differential AC Output Parameters
14-8 Test Setup for AC Output Voltage Measurements
14-9 Input Voltage Parameters
14-10 Output Skew Measurement
14-11 TCADV Minimum and Maximum Measurements
14-12 Setup and Hold Time for CAD and Control
15-1 Simple Synchronous Clocking Interface
15-2 Synchronous Clock Example, Single Direction
15-3 FIFO Operation When Tx Clock Out and Rx Clock are in Sync
15-4 Effects of Tx Out Clock Lagging Rx Clock
15-5 Effects of Rx Clock Lagging Tx Clock Out
15-6 Example Pseudo-Synchronous Mode Implementation
16-1 HyperTransport-HyperTransport Bridge Interfaces
16-2 HyperTransport Bridge Header Command Register
16-3 HyperTransport Bridge Header Status Register
16-4 HyperTransport Bridge Header Secondary Status Register
16-5 HyperTransport Bridge Header Memory And Prefetchable Base/Limit Register
16-6 HyperTransport Bridge I/O Base And Limit Register
16-7 HyperTransport Bridge Control Register
17-1 HyperTransport Double-Hosted Chain Configuration
17-2 Slave Command CSR: Key Fields In DHC Configuration
17-3 Host Command CSR: Key Fields In DHC Configuration
17-4 Sharing Double-Hosted Chain With Master/Slave Host Bridges
17-5 Non-Sharing Double-Hosted Chain
18-1 LDTSTOP# is an Input to All HT Devices Except the SMC.
18-2 LDTREQ# is an Output from All HT Devices and an Input to the SMC.
18-3 Example Wakeup Signaled by HT-to-PCI-X Bridge.
18-4 SM Request Packet Contents for Delivering STPCLK
19-1 Host-Centric HyperTransport System
19-2 A HyperTransport-Based Communications Processing System
20-1 Topology Causing Deadlock Scenario for Rows 4 and 5
20-2 Subtractive Decode in a Simple HT System
20-3 Subtractive Decode Agent Behind PCI Bridge
20-4 Subtractive Decode Agent on PCI Bus 0
20-5 Legacy Configuration Mapping for Host to HT Bridge with AGP and DRAM Controller
20-6 Deadlock Scenario 1 Topology
21-1 HT Address Space May Exceed that of the Processor and Expansion Bus
21-2 Format of the Address Remapping Capability Block
21-3 X86 Processor I/O Mapping Example
21-4 PowerPC I/O Mapping Example
21-5 Example of Direct Memory Mapping between CPU, HT, and PCI.
21-6 Prefetchable Memory Address Remapping Registers
21-7 SBNPCtl and SBPreCtl Register Format
21-8 DMA Control Field
22-1 CPU Signals Routed Between South Bridge and CPU
22-2 SM Request Sources
22-3 Legacy APIC Implementation
22-4 Format of the Interrupt Redirection Register
22-5 HT-Based Platform with IO APIC
22-6 Example X86 Platform Containing HT I/O Devices and an IO APIC
22-7 Format of X86-Based Interrupt Request Message
22-8 EOI Request Message Format
22-9 Legacy x86 Platform ” Single Processor & 8259 Interrupt Controllers
22-10 HT-based System with 8259s
22-11 Legacy INTR ” Interrupt Request and Data Packet Format
22-12 Interrupt Acknowledge Request Packet Format
22-13 Legacy A20 Mask Signal
22-14 HT A20M# Delivery
22-15 Format and Contents of the A20M SM Request Packet
22-16 SMM Signaling in Legacy Systems
22-17 SM Request Content for SMI Message
22-18 SM Message Content for SMIACT
22-19 Legacy Numeric Coprocessor Error Reporting
22-20 DOS Compatible Floating-Point Error Signaling
22-21 Example X86 System with Required DOS-Compatible FPU Error Handling
22-22 Format and Content of the SM FERR Message
