Scalable Performance

The width of the transmit and receive portion of the link (CAD signals) may be different. For example, devices that typically send most of their data to main memory (upstream) and receive limited data from the host can implement a wide path in the high performance direction and narrow path for traffic in the lesser used direction, thereby reducing cost.

The HyperTransport link combines the advantages of both serial and parallel bus architectures. HT provides options for the number of data paths implemented and for the clock rate at which data is transferred (see "Scalable Link Width and Speeds" on page 30); thus, providing scalable link performance ranging from 0.2GB/s to 12.8GB/s. This scalability is helpful to system designers. For example:

• An implementation that needs all the available bandwidth (e.g. system chipsets), can use wide links (up to 32 bits), running at the highest clock frequencies (up to 800MHz now and 1GHz in the future).

• Implementations that don't require high bandwidth but do require low power may use narrow links (as few as 2 bits) and lower frequencies (down to 200MHz).

Figure 2-9. Scalable Link Width and Speeds

HyperTransport lends itself to scaling well because:

• The high frequency bus translates to fewer pins required to transfer a specific amount of data. The same protocol is used regardless of link width.

• Differential signaling results in a very low current path to ground, thereby reducing the number of power and ground pins required for devices.

• Each additional byte lane added has its own source synchronous clock.

• HT's implementation of ACPI compliant power management and interrupt signaling is message based, reducing pin count. Note that only two additional signals, LDTSTOP# and LDTREQ#, are required for managing power.

Data Widths

HT provides scalable data paths with link widths of 2-, 4-, 8-, 16-, or 32-bits wide in each direction, as pictured in Figure 2-10 on page 31. The link width used immediately following reset is restricted to no wider than 8 bits. Later during software initialization, configuration software determines the maximum link width that can be supported in each direction and configures both devices to use the maximum width supported for each direction. See "Tuning the Link Width (Firmware Initialization)" on page 295 for details.

Figure 2-10. Link Widths Supported

Table 2-1. Signals Used for Different Link Widths

Link Widths	2	4	8	16	32
Pin Names	Number of Pins
Data Pins (CAD)	8	16	32	64	128
Clock Pins (CLK)	4	4	4	8	16
Control Pins (CTL)	4	4	4	4	4
LDTSTOP#/LDTREQ#	2	2	2	2	2
RESET#	1	1	1	1	1
PWROK	1	1	1	1	1
V HT	2	2	3	6	10
GND	4	6	10	19	37
Total Pins	26	36	57	105	199

As mentioned earlier, asymmetrical link widths are allowed in HyperTransport. For example, devices that typically send the bulk of their data in one direction and receive limited data in the other direction can save on cost by implementing a wide path in the high bandwidth direction and a narrow path for traffic in the low bandwidth direction. Note that the HyperTransport protocol doesn't change with link width. Packet formats remain the same, although it will obviously require more bit times to shift out a 32 bit value on a 2-bit link vs. a 32-bit link (16 bit times vs. 1 bit time).

Clock Speeds

HyperTransport clock speeds currently supported are 200MHz, 300MHz, 400MHz, 500MHz, 600MHz, and 800MHz. Note that 700MHz is not supported. Both rising edge and falling edges of the clock are used to clock signals. The clocking mechanism is referred to as double data rate (DDR) clocking. DDR clocking translates to an effective clock frequency that is double the actual clock frequency. In addition, because each link is dual simplex, the actual link bandwidth is quadrupled when compared to the clock rate.

Table 2-2 shows the bandwidth numbers based on symmetrical links for selected combinations of clock frequency and link width. For example, consider the bandwidth in GigaBytes/second for a 32-bit link operating at 800MHz:

• 800MHz clock with DDR = effective clock of 1,600MHz/s (1.6GTransfers/s)

• 1.6GTransfers/s x 4 bytes = 6.4GB/s

• 6.4GB/s in both directions = 12.8GB/s.

Table 2-2. Maximum Bandwidth Based on Various Speeds and Link Widths

Link Width (bits)	Bandwidth per Link(in Gbytes/sec)
	800MHz	400MHz	200MHz
2	0.8	0.4	0.2
4	1.6	0.8	0.4
8	3.2	1.6	0.8
16	6.4	3.2	1.6
32	12.8	6.4	3.2