The A20 Mask

The A20M# input forces the processor to emulate the address wrap-around at the 1MB boundary that occurs on the 8086/8088 processors. This pin should only be asserted by external logic (under software control) when the microprocessor is in Real Mode. The x86 microprocessors mask physical address bit 20 (forces it to a zero) before performing a lookup to the internal cache or driving a memory bus cycle onto the buses. For additional information, see MindShare's ISA System Architecture book, published by Addison-Wesley.

The Legacy Method of Signaling A20M#

Figure 22-13 illustrates the legacy method of signaling A20 Mask to the processor, along with methods that software has to change the A20M# signal state:

• Output pin from the keyboard microcontroller. (original source) ” The A20M# signal is connected to one of the keyboard microcontroller's local output pins. Software issues a legacy command sequence to micro controller, causing this output pin to change state.

• I/O Port 92h (introduced by IBM in PS/2 products as an alternate source) ” A bit position within a register mapped at I/O location 92h also determines the state of the A20M# signal. Software can set or clear the bit, causing the A20M# state change.

Figure 22-13. Legacy A20 Mask Signal

The HT Method of Signaling A20M#

The System Management Controller delivers state changes associated with the A20M# signal via SM Requests to the Host Bridge, which in turn delivers the change to the processor via the physical A20M# signal. Figure 22-14 illustrates this mechanism and Figure 22-15 on page 511 illustrates the contents of the SM request packet, including the value used in the SysMgtCmd field.

Figure 22-14. HT A20M# Delivery

Figure 22-15. Format and Contents of the A20M SM Request Packet