1.4 Challenging topics in communication circuits and systems

In this section we highlight some challenging topics in analogue and RF CMOS circuits and systems for wireless communications. These topics are critical factors for the implementation of future-generation ubiquitous single-chip transceivers.

1.4.1 Transceiver architecture and system-level design

There are three types of receiver architecture: heterodyne, low-IF, and zero-IF. Traditional receivers normally use the heterodyne architecture with one or two high-IF stages. Software-defined radio, however, drives the use of zero-IF receivers. The heterodyne receiver is difficult for single-chip implementation, as it requires a sharp image reject filter. The difficulties with the zero-IF structure are the DC offsets, 1/f flicker noise and second-order distortion, and the very stringent requirements for data converters. Currently a compromised low-IF architecture is most widely used. Using this type of receiver, DC offsets can be overcome and high integration achieved. The quadrature IF or baseband architecture with orthogonal Iand Q-channels is used in receivers. On the transmitter side, there is a similar development in architecture.

In the system-level design of a transceiver, the location of the data converter in the receiver chain is important for the whole system performance. In some softwaredefined radio systems, the ADC is ideally placed at the antenna. However, very large dynamic range and very high-speed converters are required and there are technological limitations on achieving this. Thus the choice between certain analogue and digital signal processing techniques must be made realistically to meet all requirements of power consumption, chip area, and reconfigurability. Several methods have been proposed to relax the requirements on ADCs, such as gain control using a variable gain amplifier (VGA) to accommodate the fixed input range of an ADC. More recently a revised low-IF receiver architecture in which the need for a complex ADC is avoided has been proposed. In this architecture, only the real part of the complex IF signal after mixers is processed, the imaginary part being ignored. The new architecture substantially simplifies the ADC design whilst retaining all the advantages of a digitised, low-IF receiver. This architectural and system level topic will be covered in Chapter 2 of the book.

1.4.2 RF, IF and analogue baseband circuits and subsystems

As discussed above, system design issues of CMOS transceiver hardware architecture should be addressed very carefully to achieve the best compromise between high programmability, low power consumption, and small chip area. A transceiver consists of several parts including a digital baseband, data converters, an analogue baseband, an IF stage, and an RF frontend. Digital baseband design involves DSP software and FPGA hardware implementations. The major advantage of DSP and FPGA is the ease of reconfigurability and programmability. Current research activities in digital baseband design are directed to further enhance computation speed and reduce power consumption. For ADC design, a key trade-off is between bandwidth and noise performance; higher bandwidth will allow more noise to enter the ADC. Recently, bandpass ΣΔ modulation techniques have been proved useful for reducing the noise in a wideband ADC.

To bring a whole transceiver onto a single chip, the key components are, however, the mixers, oscillators and filters and the LNAs in the receiver frontend and power amplifiers in the transmitter. In the baseband and IF stages the channel select filter and VGA are important. Generally, the major advantages of analogue signal processing are high speed, low power consumption and small chip area. Reconfigurability and tunability of analogue and RF circuits can also be achieved using various recent circuit techniques. Chapters 3–8 in this book will therefore focus on the analogue baseband, the IF stage and RF frontend circuits and subsystems. A review of the topics covered in these chapters is given below.

1.4.2.1 Reconfigurable analogue circuits and FPAA for the baseband and IF stages

Reconfigurable and programmable analogue circuits and systems have received much interest recently. Op-amp-based active-RC and MOSFET-C circuits have been used in transceiver baseband design and OTA-based OTA-C circuits have also been used in IF stages. Both MOSFET-C and OTA-C circuits are electronically tuneable. With some additional digitally controlled switches, the baseband and IF chains can also be made reconfigurable for multiband and multimode wireless applications. The tuneable frequency and variable gain chain can also relax the stringent requirements of speed and dynamic range on ADCs. The emerging field-programmable analogue array (FPAA) may make it possible for a whole baseband and IF stage to be fully programmable and reconfigurable. The FPAA for this purpose can be constructed using OTA-C and MOSFET-C circuit techniques. With the successful application of digitally controlled analogue baseband chains, the use of more general programmable analogue and mixed-signal arrays in multistandard transceivers, especially in analogue baseband and IF stages typically containing lowpass filters and variable gain amplifiers, seems possible in the near future. A whole programmable mixed-signal baseband array to contain the analogue FPAA, analogue-to-digital converter and digital FPGA may also be possible.

1.4.2.2 Filter design and on-chip tuning methods for applications up to RF

Filters are widely considered as the bottle-neck for ubiquitous system-on-chip communication due to the difficulties in implementing them on-chip. The use of narrowband RF filters for channel selection and image rejection has been delayed due to lack of efficient monolithic fabrication. Most of the actual systems use off-chip bulky passive filters. Major problems for active IC filters are lack of high-quality inductors, good varactors and efficient automatic tuning systems. In low-IF and zero IF transceivers, complex polyphase filters are required. Recently, much attention has been paid to the design and implementation of this type of filter. To satisfy all transceiver design requirements, many different types of filters operating over a wide range of frequencies and bandwidths are required. Popular ones are active-LC filters, OTA-C filters and MOSFET-C filters for RF, IF and baseband applications, respectively. Different filter circuits have different design challenges. For example, optimisation of LC tanks minimises the effects of loss and parasitics of on-chip inductors for active-LC filters and design of highly linear OTAs is needed for OTA-C filters. Various parasitics and large variations in on-chip component values (which can be as high as 50 per cent) lead directly to large divergence of the achieved filter response from the intended design specifications. On-chip tuning thus becomes essential and the tuning system may well be the most difficult challenge in achieving satisfactory filter performance.

1.4.2.3 RF receiver frontend modules (LNA, VCO, mixer) and chips

Low noise must be targeted in RF receiver frontend design, as the received signal is normally very weak. The high carrier frequency is another feature of the frontend. Wireless communication covers the 1–2 GHz mobile cellular range to the 5 GHz range for WLANs. Traditionally, radio-frequency integrated circuits (RFICs) were implemented in GaAs or SiGe bipolar technologies, because of their relatively high unity gain cutoff frequencies f_T (>65 GHz) and their superior noise performance. However, as the minimum feature size of CMOS devices decreases, the f_T of the transistors continues to improve to the point where it is becoming comparable to those of GaAs and SiGe processes. Deep-submicron-CMOS devices with f_T's exceeding 100 GHz and minimum noise figures (NF) less than 0.5 dB at 2 GHz have been possible. Because of these promising RF performances, together with the advantages of low cost and ease of integration with baseband digital circuitry, CMOS is becoming a viable alternative for RF applications. Recent effort has been directed to integrated inductors riding on rapid advances in IC technology. LC tanks and transformers in CMOS and even transmission lines are now possible and have performances suitable for many applications, especially short-range wireless connectivity. The success of integrating inductors on silicon chips has led to a major renewal of RFresearch activity. Various traditional RF circuits based on discrete inductors have been redesigned to benefit from on-chip inductors. In particular, transceiver frontend circuits using LC tanks such as low-noise amplifiers, oscillators, mixers and filters can now be integrated on the same chip.

1.4.2.4 RF transmit power amplifiers

Power amplifiers in the transmitter are typically working at high signal level and high carrier frequencies. Until now, power amplifiers for wireless applications were produced almost exclusively in GaAs technologies, with a few exceptions in LDMOS, Si BJT, and SiGe HBT. While CMOS provides high functionality and complexity at low cost, for an RF power amplifier, the problem of using CMOS technology is more severe than other blocks in the transceiver due to the limited voltage-handling capability. The linearity and power efficiency are lower than other technologies. Therefore, implementation of RF power amplifiers for wireless transmitters in CMOS has been one of the most challenging tasks. The design of power amplifiers in CMOS technology is affected by many factors such as low breakdown voltage of deep-submicron technologies. Several classes of power amplifiers may be chosen for different applications. On-chip power controllability or programmability is particularly important for both single and multistandard wireless applications. The output impedance matching network may be implemented either on-chip using silicon inductors or more easily off-chip as part of the antenna system.

1.4.3 Design optimisation and automatic testing techniques

Tools and methods are also important for successful optimum design and on-chip testing of transceivers and RF circuits. Advances in these areas are briefly overviewed below. These topics will be the subjects of Chapters 9 and 10 of the book.

1.4.3.1 RF design optimisation and CAD

Traditional RF design is mainly based on some empirical, trial and error methods. Complex modern integrated RF IC design can only be solved using electronic design automation tools. Two major problems in the design and optimisation of RF frontend circuits in fine-line CMOS technology are active devices that are inferior to their GaAs and SiGe counterparts, and low-quality parasitic-laden passive components owing to the use of the lossy silicon substrates. To overcome these drawbacks, the parasitic-aware synthesis paradigm has been developed. Simulated annealing is one of the key algorithms used in the parasitic-aware design and optimisation methodology. Unlike in baseband circuits, the parasitic effects are severe in RF circuits. In the case of baseband circuit design, minimizing parasitics is usually sufficient. However, the parasitics must be carefully modelled and considered as part of the design process in high-frequency circuit synthesis. If parasitics are considered as part of the design, it is difficult to find an analytic solution by hand. Thus, computer-aided RF design and optimisation must be adopted.

1.4.3.2 On-chip testing of communication ICs

There has been some growing interest in the testing of communication system-on-chip devices including analogue, mixed-signal and RF circuits. Automatic testing becomes more and more important to drive down the overall cost of communication devices due to the decidedly imperfect nature of the manufacturing process and its associated tolerances. Design for testability (DFT) has been widely accepted by industry. In today's IC design, testing issues are considered at the early design stage. Built-in-self-testing (BIST) has already been widely used in many practical electronic products and the on-chip test system concept has also been proposed for complex integrated systems. Both functional testing and parametric testing are important, with functional testing being relatively easier than parametric testing. For analogue, mixed-signal and RF circuits, testing proves much more difficult than for digital circuits due to tolerances, parasitics and non-linearities, which make testing ambiguous and computationally intensive. Analogue circuits consist of many parameters and are defined by a large set of specifications. Attempting to verify all specifications and test all parameters in the production test phase is too prohibitive, so careful planning of which specifications and parameters to test is important. To make the test results unambiguous, care must be taken on test-point selection, test-signal generation and measurement. A recent trend in test integration which promises to reduce many of the burdens of analogue testing is the use of embedded mixed-signal test cores, which are integrated circuit ‘macros’ that emulate the functions of automatic test equipment. These embedded test cores are designed to perform DC curve-tracing, oscilloscope, timing, and frequency domain measurements using compact and mostly digital integrated electronics.