9.5 Conclusions

9.5 Conclusions

The parasitic-aware design and optimisation of RF circuits has been discussed. Parasitic-aware CAD synthesis is essential in the design of CMOS RF communications circuits due to the parasitic effects that must be considered early on as part of the design.

An adaptive simulated annealing method with tunnelling and a post-optimisation PVT analysis technique have been proposed. Examples show that adaptive simulated annealing accelerates the optimisation as well as escaping from local minima more easily than with simulated annealing. Also, the post-optimisation PVT method was able to consider PVT variations in circuit optimisation with a minimal increase in iteration count.