Category list

EMMS -- EnterLeave MMX State

EMMS Enter/Leave MMX State

Mnemonic

PII

3D!

3Mx+

SSE

SSE2

A64

SSE3

E64T

EMMS

FEMMS Enter/Leave MMX State

Mnemonic

PII

3D!

3Mx+

SSE

SSE2

A64

SSE3

E64T

FEMMS

Destination/Source Orientations

Another difference between platforms has to do with the format of the assembly instructions. Depending on the processor there are typically two orientations.

Some non-80x86 processors allow the destination register to not be a source register. Thus, Register D = Register A + Register B. Or D = D + A. In C programming this is a form similar to:

D = A + B

D = D + A

The 80x86 processor family requires the destination to be one of the sources. In C programming this is similar to:

D += A

D = D + A

Proc: x86 MMX, SSE, SSE2, 3DNow!, etc.
mnemonic destination , source paddb xmm1, xmm2

Big/Little-Endian

One very important processor specification to be aware of is the endian orientation. This drastically affects how byte ordering affects data orientation. Depending on the processor and its manufacturer, data structures larger than a byte are typically arranged in one of two orientations:

Little-endian
Big-endian

One interesting aspect is that for either little or big endian, the 8-bit byte both have an identical bit ordering of bits {07}. The MIPS processors (as a default) and the 80x86 are little-endian, but the Motorola 68000 and the PowerPC RISC microprocessor are big-endian.

image from book
Figure 3-9: Data conversions

Little-endian is linear just like memory, so every more significant byte would be the next (incremental) addressed one in memory. For the size of a data word in big-endian, every more significant byte would be the previous (decremental) addressed one in memory.

In big-endian the most significant byte is first in memory and it progresses down to the least significant byte; the cycle repeats for the next block. In the following diagram, the data in memory is blocked into groups of 128 bits (16 bytes).

image from book
Figure 3-10: Big-endian and little-endian byte orientations in relation to memory

The Intel 80x86 processor is a little-endian based processor. That is, the memory is laid out in a linear fashion so the first byte contains the LSB (least significant bit). For example, as Figure 3-11 shows, a dword has the lower bits (70) in the first byte (#0) and bits (3124) in the fourth byte (#3). This pattern is repeated over and over.

image from book
Figure 3-11: Visible connections between individual bytes and the left shift of a 32-bit data element

In the C programming language, use the following shift to the left by one for a 32-bit data word (int).

a = a << 1;

Dealing with endian orientation can sometimes be confusing, especially if you primarily work in little-endian and then need to convert data to the form of big-endian. This makes perfect visual sense for bigendian because the fourth byte contains the least significant bit (LSB) and data is shifted to the left toward the most significant bit (MSB). For little-endian the same shift in C magnifies the value by a factor of two for each bit but visually it makes no sense because the LSB is on the left. By using a mirrored reflection it then becomes clear.

At this point this should be enough conversation about endian orientation of memory until you get to Chapter 6, "Data Conversions," where this is discussed more thoroughly.