D.5 Floating-Point Registers

The Itanium architecture defines 128 floating-point registers (Fr₀ Fr₁₂₇), which are 82 bits in width and can thus accommodate expanded forms of single- or double-precision IEEE values and also signed or unsigned 64-bit integers:

Unlike the general registers, the floating-point registers do not have an associated invalidity bit; instead, there is room in the coding of the data representation for a special invalidity value called NaTVal (not a thing value). NaTVal informs the CPU hardware that the contents of the floating-point register are invalid.

Table D-4 gives the nomenclature and standardized uses of the set of Itanium floating-point registers. A register is constant if its value is permanently defined at the hardware level. A register is scratch if it may be freely used by a routine at any calling level (caller must save anything important). A register is preserved if a calling routine depends on its contents (any called procedure must save and restore its contents for its caller).