13.6 Determining Extensions and Implementation Version

Once an architecture acquires extensions, the need arises for compilers, operating systems, and system boot-up code to be able to determine the characteristics of a particular machine configuration.

The Itanium architecture provides a set of cpuid registers (Appendix D.8) that software can read. The cpuid register 3 has 8-bit fields specifying the architecture revision, the processor family, the processor model number, the processor revision number, and the highest implemented index number for the cpuid registers (at least 4).

Fields in cpuid register 4 indicate application-level features as a set of flag bits for presence (1) or absence (0) of each feature. For example, bit 0 indicates whether the processor implements the brl instruction (e.g., Itanium 2 processor) or the operating system must provide emulation when that opcode causes an exception (e.g., initial Itanium processor). Similarly, bit 2 indicates whether the 16-byte atomic operations (ld16, st16, and cmp8xchg16) are implemented.