| Figure 1-1 shows a typical PA-RISC processor. The architecture provides for a translation lookaside buffer (TLB), which is used to assist in translating virtual addresses to physical addresses. The inclusion of a cache is optional, but most PA-RISC processors do have at least some amount of cache. The architecture also provides for assist processors such as a floating-point processor to assist in complex operations. Figure 1-1. Processor Block Diagram 
Central Processing Unit The CPU itself contains the system's register set, control logic, and execution logic. The register set, discussed in detail below, is where all of the computation takes place in the processor. The only instructions that access memory are explicit load and store operations. Thus, to operate on a value, the value must be loaded, manipulated, then stored. Frequently used data is kept in registers to bypass the load and store operations. The CPU's control logic is responsible for fetching and decoding instructions. The CPU can prefetch instructions, and multiple instructions are pipelined within the CPU for parallel execution. The execution logic performs the actual operations on the data. This section of the CPU consists of the arithmetic logic unit (ALU), shift and merge units, mask registers, and a variety of other hardware for executing the instructions. PA-RISC provides for four different privilege levels that determine what operations the CPU is permitted to perform and what data it can access. The HP-UX kernel uses only two of these privilege levels: 0 for kernel and 3 for user. The system checks access rights on a per-page basis. Each page of memory in the system has an Access Rights entry, which indicates privilege levels required to read, write, or execute that page. The system also provides for a gateway instruction, which is used for promotion from one privilege level to another. This instruction is used by the kernel when transitioning from user mode to kernel mode. This process is discussed in detail in Chapter 3. Translation Lookaside Buffer The TLB is used in translating virtual addresses to physical addresses. Each entry in the TLB holds a virtual page number, the corresponding physical page number, and the access rights for that particular page. The system may use separate TLBs for instructions (ITLB) and data (DTLB), or it may use a combined TLB. PA-RISC version 2.0 includes provisions for variable-sized pages. Prior to PA-RISC 2.0 all pages were a fixed 4 KB. PA-RISC 2.0 can use pages ranging from 4 KB to 64 MB. This allows for more efficient use of the TLB when very large data structures are used. A large data structure can be placed in a single large page and will use only one TLB entry rather than requiring several. When an instruction accesses a particular virtual page, that page is looked up in the TLB to find the corresponding physical address and the access rights. If a matching entry is not present, a TLB miss interruption is generated. The system must then look up the correct entry in the Page Directory (PDIR), insert the entry into the TLB, then restart the instruction. The details of how this happens are covered in Chapter 6, "Managing Memory." Cache PA-RISC uses a visible cache architecture. The processor has instructions to explicitly manipulate the cache, flushing or invalidating cache entries where required. Systems can have separate instruction and data caches, or they may have a single combined cache. In order to have the required data in the cache whenever possible, the cache is capable of prefetching data and instructions. To determine which data should be fetched, the PA-RISC processor uses branch prediction to guess which way conditional branches will go. Compilers can code a prediction into branch instructions. For example, if a branch is used in a loop, and the loop will run for 100 iterations, then the end-of-loop branch will be taken 100 times, not taken just one time. The compiler can indicate to the processor that it is more likely that the branch is taken, and the cache prefetch circuitry can then prefetch the correct instructions. PA-RISC 2.0 also adds a dynamic branch prediction functionality. The processor keeps track of how many times a branch actually went the way that the compiler predicted. If the branch prediction indicator is wrong more than right, then the system starts prefetching the opposite of the way the branch prediction indicates. In a multiprocessor system, the cache must also be aware of the memory activity of other processors. This is called cache coherence. The cache circuitry continually monitors the system bus for load and store instructions from other processors. In this way, it will know if the data in the cache is no longer valid due to access from a different processor. Assist Processors The PA-RISC architecture provides for extensibility in the form of assist processors. Two kinds of assist processors are defined: special function units (SFUs) and coprocessors. An SFU is a hardware module that has direct access to the CPU's general registers but operates outside of the CPU's execution unit. Although the architecture defines how SFUs are to be implemented, none are currently used. A coprocessor is also an assist processor, but it is less closely coupled to the CPU. It has its own set of registers, and data must be explicitly passed to and from the coprocessor for processing. An understanding of the assist processors is not required for an understanding of the kernel, so we do not go into detail beyond this brief mention. Suffice it to say that PA-RISC processors do have a floating-point coprocessor, and if you find yourself looking at assembly code, you may occasionally see references to it. | 