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7.5 Asynchronous Versus Synchronous Counters

In the designs described in the previous sections, we used a synchronous design style. That is, we constructed all of the example counters from flip-flops controlled by a common clock signal (labeled count in the figures). In a fully synchronous counter, the storage elements simultaneously examine their inputs and determine new outputs. This is the preferred way to build counters, but there are other approaches we will examine in this section.

7.5.1 Ripple Counters

Some counters avoid the global clock altogether. These elements count by propagating or rippling the decision to change state from one storage element to an adjacent element. Hence these counters are called ripple counters, and we study them next.

Example Three-Bit Binary Ripple Counter

 

Figure 7.37 shows a 3-bit binary ripple counter constructed from T flip-flops (the reset logic is not shown). The lowest-order (most rapidly changing) bit is the leftmost. The output from one stage drives the clock of the next stage to the right.

The timing waveform for a typical count sequence is shown in Figure 7.38.

Compare it with Figure 7.17, the timing diagram of an equivalent synchronous counter. In the ripple counter the state changes do not all take place on the falling clock edge but continue into the next high time of the clock. This points out a serious problem with ripple-type circuits: the propagation through the counter takes longer to reach its next output state as more stages are added to the counter.

In effect, the ripple counter computes its next state in a serial fashion, rather than in parallel as in the implementation of Figure 7.16. Since the state transitions are not crisp, external logic reading the current state as an input can glitch or "spike" in an undesirable manner. Despite the simpler hardware, you should never be tempted to implement a counter in this fashion.

Cascaded Counters Cascading is the process of combining several smaller-bit-width components into a larger-bit-width function. As you have seen, an 8-bit shift register can be constructed by wiring together two 4-bit registers. You can use a similar strategy to build wider counters from multiple 4-bit slices. Even though the counter components are implemented internally using synchronous techniques, the components are wired together in a series ripple fashion. These are cascaded counters.

Figure 7.39 shows an 8-bit cascaded counter. Shortly after the rising edge in which the low-order counter enters the state 1111, the RCO, ripple carry output, is asserted. This signal enables the next higher stage for counting. On the next rising edge, the low-order bits enter state 0000, the high-order bits count by 1, and the first RCO signal is unasserted.

The detailed sequence of events is given in the timing waveform of Figure 7.40.

First, the low-order counter enters the state 1111. Second, the RCO is asserted. Third, the higher-order stage counts by 1.

If ripple counters are such a bad idea, why do we allow rippling here? The answer is that the cascaded counters of Figure 7.39 are still synchronous. The counter's internal logic computes the RCO signal in parallel, simply by ANDing together the current-state bits. The count takes place on the rising edge of the clock. As long as there is enough time between rising edges for RCO to be asserted by the lower-order counter and recognized by the higher-order counter, the cascaded counters function properly. This is a perfectly acceptable use of a ripple signal.

7.5.2 Synchronous Versus Asynchronous Inputs

In Chapter 6 we described some of the dangers in using asynchronous inputs to otherwise synchronous systems. In general, you should try to avoid components with asynchronous inputs.

The ubiquitous 74163 counter illustrates the power of synchronous inputs. In addition to its internal synchronous implementation, it provides synchronous clear and load signals. This makes it ideal for implementing more complex count sequences with a beginning offset or limiting cutoff.

Example Starting Offset Counter  Suppose we need to implement a counter that follows the sequence 0110 through 1111 and then repeats. The RCO signal, in conjunction with a synchronous load input, can implement this function easily.

The logic is shown in Figure 7.41.

The RCO signal, when asserted, is negated and used to drive the active low load input. If the desired starting state is placed at the parallel load inputs, it will be entered on the next rising edge of the clock.

This counter is self-starting. Resetting clears the counter to 0000. Although it starts off in an invalid state, it reaches the desired sequence within six clock periods.

The timing waveform is given in Figure 7.42. The signal (the complement of RCO) is asserted when the counter enters state 1111. On the next rising clock edge, the counter enters state 0110.

Example Cutoff Limit Counter Similarly, we can construct a counter with a cutoff limit by using the synchronous clear signal. For example, we can use the logic of Figure 7.43 to implement a counter that begins at 0000 and sequences through to 1101 before restarting.

When the counter enters the cutoff state, the active low signal is asserted. This forces the counter into the zero state on the next rising edge.

Figure 7.44 shows the timing diagram. When the counter reaches 1101, it enters the cutoff state, goes low, and the next state is 0000.

Dangers of Asynchronous Inputs The designs of Figure 7.41 and Figure 7.43 would not be possible if the clear and load inputs were asynchronous. We use external logic to recognize the offset or cutoff state, to assert a control input that leads to an out-of-sequence new state. In these synchronous designs, the state does not change until the next rising clock edge.

If the control inputs were asynchronous, the state change would have happened as soon as the control input was asserted, independent of the clock. This violates a fundamental assumption of synchronous systems-that the state changes at clocking events and not at other times.

Let's reexamine the counter of Figure 7.43, but this time implemented with the TTL 74161 counter. This device is identical to the 74163, except that the clear signal is asynchronous.

Compare the timing diagram of Figure 7.45 with that of Figure 7.44.

The signal is obviously a short-duration pulse, and state 1101 is held for a much shorter time than any other state. In effect, if we consider the counter to advance from one state to the next on every rising clock edge, then the behavior of Figure 7.45 actually shows the counter advancing from 1100 to 0000, passing through 1101 in an instant. This is obviously not the behavior we desired.

Asynchronous inputs should be used only for situations like power-on reset. Never use them to implement state transitions. As a designer, you should always be aware of the behavior of the catalog parts you select. Remember to choose the right parts for the job at hand.

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This file last updated on 07/14/96 at 16:36:05.
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