69. | What is Sarbanes-Oxley[q]

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Exercises

1. (Sign and Magnitude Numbers) Perform the following binary additions assuming the numbers are in sign and magnitude form: 0001 + 0100

1111 + 0010
0011 + 1010
1011 + 1010

2. (Ones Complement Numbers) Perform the same binary additions as in Exercise 5.1, but this time assuming the numbers are in ones complement form.
3. (Twos Complement Numbers) Perform the same binary additions as in Exercise 5.1, but this time assuming the numbers are in twos complement form.
4. (Number Representations) Implement a combinational logic circuit that converts 4-bit sign and magnitude numbers into corresponding 4-bit twos complement numbers. Draw an input/output conversion truth table, intermediate K-maps, and your minimized two-level logic description.
5. (Number Representations) Implement a combinational logic circuit that converts 4-bit sign and magnitude numbers into corresponding 4-bit ones complement numbers. Draw an input/output conversion truth table, intermediate K-maps, and your minimized two-level logic description.
6. (Number Representations) Implement a combinational logic circuit that converts 4-bit ones complement numbers into corresponding 4-bit twos complement numbers. Draw an input/output conversion truth table, intermediate K-maps, and your minimized two-level logic description.
7. (Number Representations) Implement a combinational logic -circuit that converts 4-bit ones complement numbers into corresponding 4-bit sign plus magnitude numbers. Assume that -0 in ones complement maps into -0 in sign plus magnitude. Draw an input/output conversion truth table, intermediate K-maps, and your minimized two-level logic description.
8. (Number Representations) Sign and magnitude and ones complement representations have two zeros, while twos complement numbers have only one representation for zero. What problem does this present for converting from twos complement to either of the other representations? How might this be handled in a practical conversion circuit?
9. (Subtraction Logic) The truth table for a 1-bit combinational binary subtractor, analogous to the half adder, computing D(ifference) = A minus B, with BL (borrow-from-left), is

Design a 1-bit combinational binary subtractor, comparable to the full adder, with two data inputs (A, B), a borrow from the right input (BI), a borrow request to the left output (BL), and a difference output (D).
Show how your design can be cascaded to form multibit-subtractors.
Does the subtractor work correctly for negative twos complement numbers?
How is a subtraction underflow condition indicated?

10. (Adder/Subtractor Logic) Design a fully combinational adder/subtractor that can be cascaded to form a multibit circuit. The inputs are data inputs A, B, carry-in CI, and borrow in BI. The outputs are data output F, carry-out CO, and borrow from left
BL. A mode input M = 0 indicates addition and M = 1 indicates subtraction. Can the carry and borrow inputs and outputs be combined?
11. (Adder Design) Using comparators, multiplexers, and binary adder/subtractor logic blocks, design a 4-bit sign and magnitude adder (that is, one sign bit and three data bits). Include an overflow indicator in your design.
12. (Remainder Function) Design a combinational circuit with three data inputs D2, D1, D0, two control inputs C1, C2, and two outputs R1, R0. The R1, R0 should be the remainder after dividing the unsigned binary number formed from D2, D1, D0 by the unsigned binary number formed by C1, C0. For example, D2, D1, D0 = 111, C1, C0 = 10, then R1, R0 = 01 (7 divided by 2 yields a remainder of 1). Note: Division by zero will never occur-take advantage of don't-care conditions in this case.

13. (Multi-Bit Adders) Figure 5.14 shows how to use 4-bit adders and a 4-bit carry look-ahead unit to implement a fast 16-bit adder.

(

)

14. (Carry Select Adder) Consider a 16-bit adder implemented
with the carry select technique described in Section 5.2.3. The adder is implemented with three 8-bit carry look-ahead adders and eight 2:1 multiplexers. Estimate the gate delay and compare it against a conventional 16-bit ripple adder and a 16-bit carry look-ahead adder.
15. (Carry Select Adder) Argue why, using explicit 8-bit test cases, the implementation of C8 in Figure 5.15 is correct.
16. (ALU Design) Implement to the gate level an ALU bit slice with three operation selection inputs, S2, S1, S0, that implements the following eight functions of the two data inputs A and B (and carry-in Cn):

Assume a simple ripple carry scheme between bit slices.

17. (ALU Design) Implement to the gate level an ALU bit slice with three selection inputs, S2, S1, S0, and a logic/arithmetic mode input M, that implements the following 16 functions of the two data inputs A and B (and carry-in Cn):

Assume a simple ripple carry scheme between bit slices.

18. (ALU Design) Revise your design for the ALU of Exercise 5.16 to include carry look-ahead logic that can operate across 4 bits.
19. (ALU Design) Revise your design for the ALU of Exercise 5.17 to include four-bit carry look-ahead logic.
20. (ROM-Based ALU Design) Describe how a two-output ROM can be used to implement the ALU bit slice of Figure 5.19. Give a block diagram showing how a 4-bit ALU can be implemented from four cascaded ROMs. In terms of the total count of ROM bits, how does the bit slice approach compare with a solution that uses a single ROM with full 4-bit data inputs and outputs?
21. (ALU Design) Verify that the multilevel circuit of Figure 5.23 implements the ALU specification of Figure 5.18. Do this by expanding the circuit into its equivalent two-level sum of products expressions for C0 and Fi. Then show that the truth table/K-map for these expressions is compatible with the truth table of Figure 5.19.
22. (BCD Addition) Perform the following binary additions assuming the numbers are in BCD form:

23. (BCD/Binary Adder Design) Design a 4-bit circuit that can perform either BCD or binary addition under the control of a mode setting, M. When M = 0, the circuit's outputs implement binary addition. When M = 1, the outputs are BCD addition. Your solution should require minimal changes to the circuit of Figure 5.27.
24. (Combinational Multiplier) Verify that the operation of the combinational multiplier of Figure 5.28 is correct by tracing all intermediate signals for the multiplication of 11 (10112) by 13 (11012).
25. (Combinational Multiplier) Verify that the operation of the combinational multiplier of Figure 5.29 is correct by tracing all intermediate signals for the multiplication of 11 (10112) by 13 (11012).
26. (Combinational Multiplier) Verify that the hardware of Figure 5.35 correctly computes the product of 242 by 140 by labeling all outputs with the actual bit patterns that would be computed at each stage of the circuit.
27. (Combinational Multiplier) What is the worst-case propagation delay through the combinational multiplier of Figure 5.28, assuming the hardware is implemented with 12 full adders as in Figure 5.7?
28. (Combinational Multiplier) Suppose that the 8-by-8 multiplier of Figure 5.35 is implemented with three 74S181 ALUs and a 74S182 carry look-ahead unit (the multipliers and the full adders remain unchanged). Analyze the typical and worst-case delays by referring to your TTL databook. How does the delay compare with those computed at the end of Section 5.6?
29. (Combinational Multiplier) Assume that you have a 4-by-4 -magnitude multiplier available as a primitive building block. -Discuss the design issues in building a 4-by-4 twos complement multiplier. Consider such issues as (a) determining the signs of the inputs and outputs, (b) putting the inputs into the appropriate form for the magnitude multiplier, and (c) putting the magnitude multiplier's output into a form suitable for twos complement -representation.
30. (Combinational Divider) Design a combinational divider, following the same general approach as used for the combinational multiplier of Section 5.6. Of course, this time you will use binary subtractors rather than adders.
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