RISC-Based Server Processors


Historically, RISC-based servers have dominated the eight-way and larger server categories. RISC-based servers are so named because their processors use a design known as reduced instruction set computer (RISC). RISC processors use customized instruction sets tailored to the tasks the processor is designed to do, separate instruction and data caches, instruction pipelining, and superscalar operation to permit multiple instructions to be performed at the same time.

At one time, the differences in performance between RISC and CISC designs such as x86 processors was profound. However, starting with sixth-generation processors such as the Pentium Pro and its many descendents, x86 processors have adopted many RISC techniques to improve performance. The EPIC processor architecture used by the Itanium family has elements of both RISC and CISC designs. At the same time, the clock speeds of Itanium 2 processors have matched those offered by the fastest RISC processors, and x86 processors offer considerably faster clock speeds.

Note

When gauging processor performance, pure clock speed is only one factor in gauging a chip's overall performance.


As a result of the performance gains in x86-based chips, several families of RISC-based processors, including the Alpha, PA-RISC, and MIPS R1xxxx will be phased out in the next year or two. While RISC technologies dominate embedded computing, RISC is no longer the undisputed champion of network servers. For this reason, much of this book is focused on Intel and AMD-based system designs. The following sections provide additional details about major RISC-based sever processor families.

Alpha

The Alpha processor family is often referred to as the DEC Alpha because it was originally developed by one-time powerhouse Digital Equipment Corporation in 1992 as the Alpha 21064. The code name EV applied to various Alpha designs is short for "extended VAX," as the Alpha was originally intended to run DEC's VAX operating system.

Major features of the Alpha architecture include the following:

  • Native 64-bit design from the start; other 64-bit RISC chips are developments of 32-bit designs

  • Built-in math coprocessor

  • Out-of-order execution (starting with the 21264 EV6 processor of 1998)

  • EV6 bus licensed to AMD and used for the AMD Athlon, Athlon MP, and other processors

The success of the AMD Athlon family indicates the fundamental strength of the Alpha design as well as its biggest weakness: The Alpha uses a short, very efficient pipeline, which makes it able to handle frequent changes in instructions and data. However, the shorter the pipeline, the harder it is to scale the processor to higher clock speeds. Consequently, while the Alpha processor offered very competitive clock speeds in the late 1990s, it fell behind compared to other RISC designs such as PowerPC or x86 and Itanium 2based chips.

However, the major reason for Hewlett-Packard's decision to stop selling AlphaServers in 2006 is that Hewlett-Packard has three 64-bit server platforms. Hewlett-Packard had already decided to phase out its PA-RISC 8x00-based platforms, such as the Hewlett-Packard 9000 and Superdome series, because of its co-development with Intel of the Itanium processor family. When Hewlett-Packard purchased Compaq in 2001, Hewlett-Packard found itself with another unwanted RISC processor family that Compaq had already decided to abandon by 2004. In effect, Hewlett-Packard's purchase of Compaq gave the Compaq/Hewlett-Packard AlphaServer line a two-year reprieve that is now coming to an end. The latest AlphaServers use the 21364 processor.

Compaq, and now Hewlett-Packard, have offered AlphaServers in four product lines, as detailed in Table 2.33:

  • DS Entry-level (1 or 2 processors)

  • ES Midrange (4 to 8 processors)

  • GS High-end (8 to 32 processors)

  • SC Server clusters

Table 2.33. Compaq/Hewlett-Packard AlphaServers

AlphaServer System

Base Processor/Chip

Max. CPUs

Max. Clock Speed

DS Series

DS10

21264

1

600MHz

DS10L

21264

1

600MHz

DS20E

21264

2

833MHz or 667MHz

DS20L

21264

2

833MHz

DS25

21264

2

1GHz

ES Series

ES40

21264

4

667MHz or 833MHz

ES45

21264

4

1GHz or 1.25GHz

ES47

21364

4

1GHz

ES80

21364

8

1GHz

GS Series

GS80

21264

8

1.25GHz

GS160

21264

16

1.25GHz

GS1280

21364

16

1.15GHz

GS320

21264

32

1.25GHz

SC Series

SC20

21264

256

833MHz

SC45

21264

4096

1.25GHz


Hewlett-Packard is not the only source for AlphaServers or workstations, however. Microway (www.microway.com) offers customized Alpha-powered systems that use the 21264 Alpha processor. Microway took over support and warranty service for nonHewlett-Packard Alpha systems in 2001 when API (a joint venture between Compaq and Samsung, started in 1998 to manufacture and support Alpha processors and systems) quit the Alpha business.

For technical details of the differences in Alpha processors, see Table 2.3, p. 26.


PA-RISC 8xxx

Hewlett-Packard's PA-RISC 8000, introduced in 1996, was the first 64-bit version of its PA-RISC processor line, which was first used in the original 32-bit form in the Hewlett-Packard 3000 minicomputer line starting around 1989.

The PA-RISC 8xxx family has undergone only relatively minor design changes since it was first introduced. The major features of the PA-RISC 8000 include the following:

  • Two separate instruction caches to permit fast and slow instructions to be executed separately

  • Pipelining

  • Superscalar execution

  • No on-chip L1 cache

Improvements added to later versions include the following:

  • Better branch prediction and larger cache (PA-8200)

  • Onboard L1 cache, bigger branch history table, and translation lookaside buffer (PA-8500)

  • Faster clock speeds with improved cache design (PA-8600)

  • Even faster clock speeds with data prefetch and larger translation lookaside buffer (PA-8700)

  • Dual-core design with off-chip L2 cache and faster bus (PA-8800)

  • Faster L2 cache with improved error detection and correction (PA-8900)

Hewlett-Packard uses the Hewlett-Packard 9000 brand for its PA-RISCbased server product line. Current Hewlett-Packard 9000 servers are listed in Table 2.34

Table 2.34. Current Hewlett-Packard 9000 Servers

Model

Processor

Processor Range

  

High-end

Superdome

PA-8900, Itanium 2[1]

4-32, 4-64, 12-128

  

Midrange

rp7420-16

PA-8900 or PA-8800

2-16

rp8420-32

PA-8900 or PA-8800

2-32

  

Entry-level

rp3410-2

PA-8900

1-2

rp3440-4

PA-8900

1, 2, or 4

rp4410-4

PA-8900

1, 2, or 4

rp4440-8

PA-8900

2, 4, 6, or 8


[1] Can be mixed in the same server within separate hard partitions.

For more information about current Hewlett-Packard servers, see the Hewlett-Packard website, at www.hp.com.

For more information about PA-RISC hardware and software, past and present, see the OpenPA website, at www.openpa.net.

For technical details of PA-RISC 8xxx processors, see Table 2.4, p. 28.


MIPS R1xxxx

Although the MIPS R-series is associated with SGI, it was actually developed by MIPS Computer Systems in 1985. SGI bought MIPS in 1991 after MIPS ran into financial trouble during the development of the world's first 64-bit microprocessor, the R4000. After several other 64-bit processors were developed in various series, the R10000 processor was introduced in 1995 as an improved version of the R8000 and was used by many companies besides SGI.

The R10000 processor has the following major features:

  • Superscalar design

  • Out-of-order execution

  • Improved integer performance (compared to the R8000)

SGI had planned to switch from MIPS to Itanium processors in the late 1990s, but when the Itanium was delayed, SGI was forced to continue to develop the R10000 design with subsequent versions:

  • Faster clock speeds due to reduced die size (R12000)

  • DDR SDRAM support in off-chip cache and faster FSB (R14000)

  • Larger data and instruction caches and further die shrink for even greater speed (R16000)

Currently, SGI uses the MIPS R16000 in its SGI Origin 350 technical servers and Origin 3000 supercomputers. These systems, which run SGI's IRIX implementation of UNIX, offer highly modular and expandable designs and more closely resemble server clusters in a box than a conventional multiprocessor server. For more information, visit www.sgi.com/products/servers/origin/.

The other major vendor currently offering MIPS-based servers is Hewlett-Packard. Its NonStop S-series line of high-availability servers uses matched pairs of R12000, R14000, or R16000 processors running in lockstep, depending on the model. See www.hp.com for details.

Both Hewlett-Packard and SGI are expected to eventually move completely to Itanium-class processors for their entire product lines. Most of SGI's current servers have already moved to Itanium 2, and Hewlett-Packard is transitioning its AlphaServer and Hewlett-Packard 9000 (PA-RISC) users to Itanium 2 systems. Hewlett-Packard also offers a line of NonStop servers that use Itanium 2 processors.

For technical details of the MIPS 1xxxxx series of processors, see Table 2.5, p. 28.


For more information about Itanium, see "Itanium and Itanium 2 Processors," p. 121.


Power Architecture

The most successful RISC processor vendor appears to be IBM. It continues to develop two distinct families of RISC-based processors: the PowerPC, discussed in the following section, and the PowerPC's big brother, Power Architecture (discussed in this section).

Power Architecture processors are known as Powerx processors, ranging from the original 32-bit Power1 (RIOS) processor used by the RS/6000 line of servers and computers in 1990 to the current Power5+.

Early Power processors used multichip designs. However, the Power2 SuperChip (also known as the P2SC) was the first single-chip Power Architecture processor, and it was the last to feature 32-bit operation. Its major features included the following:

  • Superscalar operation

  • Two integer and two floating-point calculation units

  • Additional math instructions

The Power3 added the following:

  • 64-bit instructions derived from the PowerPC, making the Power3 compatible with both 32-bit and 64-bit instructions

The Power4 added the following:

  • Support for AS/400 instructions (derived from AS/400-specific PowerPC chip projects), enabling the Power4 to run in both RS/6000 and AS/400 systems

  • Dual-processor cores

  • Instruction grouping to put related instructions together for faster operation

The Power5 adds the following:

  • Improved L3 cache speed

  • Dynamic thread prioritizing (The processor determines which process threads need the most attention and uses dynamic resource balancing to keep conflicting programs on different processor cores.)

  • Simultaneous multithreading (SMT) (The processor runs two processes at the same time on the same processor core; this is a similar concept to Intel's HT Technology.)

  • Processor virtualization (This enables multiple operating systems and applications to run on a single server.)

The Power5+ is a die-shrunk version of the Power5.

Current eServer Open Power and System p5 IBM servers that use Power chips are listed in Table 2.35. Power chips are also used in other product lines, including the iSeries integrated business system.

Table 2.35. IBM Power Servers

Model

Processor

Processor Range

eServer Open Power[1]

710 Express

Power5

12

710

Power5

12

720 Express

Power5

2, 4

720

Power5

1, 2, 4

System p5[2]

505

Power5

12

510

Power5

12

520

Power5+

12

550

Power5+

2, 4

550Q

Power5+

4, 8

570 Express

Power5

28

570

Power5

216

575

Power5

8, 16

590

Power5

832

595

Power5

1664


[1] Runs Linux (Red Hat or SUSE).

[2] Runs AIX 5L (IBM implementation of UNIX) or Linux (Red Hat or SUSE).

For technical details of the IBM Power2 SuperChip through Power5 series of processors, see Table 2.6, p. 30.


PowerPC

The PowerPC chip family, originally introduced in 1992, is based on the Power Architecture Power family. PowerPC chips were originally developed as single-chip versions of the multichip Power1 processor that could be used in other IBM products in a cooperative effort between IBM, Apple, and Motorola.

The 32-bit PowerPC chip 604 was used in several servers manufactured by Apple, Motorola, and IBM, among others. Windows NT was available for early PowerPC systems but was quickly discontinued.

The 604's major features included the following:

  • Four-instruction superscalar execution

  • SMP (dual-processor) support

The 604e added larger instruction and data caches.

The 740 and 750 are members of the G3 family and were the first commercially successful 64-bit PowerPC chips:

  • The 740 lacks support for L2 cache.

  • The 750 can use L2 cache on the processor cartridge.

Both also support 32-bit PowerPC code and were used in Apple PowerMac G3 servers.

The 7400 processor (also known as the G4) was manufactured by Freescale (Motorola's former processor division) and was co-designed by Motorola and Apple. IBM did not participate in its design. The G4/7400's major features include the following:

  • 32/64-bit operation

  • AltiVec "Velocity Engine" vector processing unit

  • Improved SMP

  • 64-bit math coprocessor

The G4/7400 was used in Apple PowerMac servers.

The latest PowerPC processor family, the 970, is also known as the G5. It was developed by IBM. Major features of the G5/970 include the following:

  • IBM's Power4 processor core

  • Integrated AltiVec vector processing unit

The 970FX is a die-shrunk version of the 970. The 970MP is a dual-core version. All 970-family processors have been used in Apple PowerMac G5 xServe servers. The 970 is also used by IBM's BladeCenter JS20 server blade.

The long-term future of PowerPC chips at the server level is questionable because Apple has switched to Intel Core processors for its latest Macintosh products. However, PowerPC chips continue to be popular in video game and embedded applications, and IBM may continue to use them in its own server products.

For more information about PowerPC processors, see the IBM website, at www.ibm.com, and the Freescale website, at www.freescale.com. For more information about PowerPC-based servers, see the Apple website, at www.apple.com.

For technical details of the PowerPC series of processors, see Table 2.7, p. 30.





Upgrading and Repairing Servers
Upgrading and Repairing Servers
ISBN: 078972815X
EAN: 2147483647
Year: 2006
Pages: 240

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