The following tables provide you with a quick overview of the processor families that are considered in this chapter: Intel, AMD, Alpha, PA-RISC, MIPS, PowerPC, and Power. Note The Alpha, PA-RISC, and MIPS processor lines are in the process of being phased out by their respective manufacturers. However, they will continue to be available at least through 2006, and existing systems will likely require support for several years to come. Table 2.1 lists the major specifications of Intel processors that have been used as server processors, starting with the Intel Pentium Pro. Table 2.1 includes both processors originally designed as desktop processors and those designed as server processors. Because Intel uses the same brand name for processors with distinctly different features, the code name used to refer to a particular server processor's core design is provided in parentheses.
Note Table 2.1 excludes the 8088 through 80486 and Pentium processors, none of which are likely to be encountered today. It also excludes laptop-specific CPUs (such as the Pentium M) and the Intel Celeron family of low-cost and reduced-cache versions of the Pentium, Pentium II, Pentium III, and Pentium 4 processor families; the Celeron family is marketed exclusively as a desktop processor and is thus not likely to be encountered in a server. Table 2.2 lists the AMD processors, starting with the AMD Athlon MP, that have been used in servers. As with Table 2.1, the core design is listed in parentheses in the Processor column.
Note Table 2.2 omits the Pentium-equivalent K5 and K6 families; laptop-specific versions of all CPUs; the Duron and Sempron families, which are lower-performance, low-cost versions of the Athlon; and the Athlon XP and Athlon 64 processors, which are sold strictly as desktop processors. Note Note in Table 2.1 that the Pentium Pro processor includes 256KB, 512KB, or 1MB of full-core-speed L2 cache in a separate die within the chip. The earlier Pentium II/III processors include 512KB of half-core-speed L2 cache on the processor card. Pentium II PE and Pentium IIIE and IIIB processors include full-core-speed L2 cache integrated directly within the processor die. The later Pentium 4A includes 512KB of on-die full-core-speed L2 cache. The transistor count figures in Table 2.1 do not include the external (off-die) 256KB, 512KB, 1MB, or 2MB L2 cache built in to the Pentium Pro, Pentium II/III, or PII/PIII Xeon, or the L3 cache in the Itanium. The external L2 cache in those processors contains an additional 15.5 million (256KB), 31 million (512KB), 62 million (1MB), or 124 million (2MB) transistors in separate chips, whereas the external 2MB or 4MB of L3 cache in the Itanium includes up to 300 million transistors. Table 2.3 lists the major features of Alpha processors used in servers from 1996 to the present.
Table 2.4 lists the specifications for PA-RISC 8xxx-series server processors from 1996 to the present.
Table 2.5 lists the specifications for MIPS server processors from 1994 to the present.
IBM's line of Power architecture processors for the RS/6000 and p5 server lines provided the basis for the PowerPC series of processors. Table 2.6 lists the specifications for Power Architecture server processors from 1996 to the present.
Table 2.7 lists the specifications for PowerPC server processors from 1995 to the present.
Note PowerPC processors not listed are designed for use in desktop or notebook computers.
Server Processor SpecificationsServer processors, like all other processors, can be identified by two main parameters: how wide their data path is and how fast they are. The speed of a processor is a fairly simple concept. Speed is counted in megahertz (MHz) and gigahertz (GHz), which means millions and billions, respectively, of cycles per secondand faster is better. The width of a processor is a little more complicated to discuss because three main specifications in a processor are expressed in width:
Note that the processor side bus (PSB) is also called the front-side bus (FSB) or CPU bus. These terms all refer to the bus that is between the CPU and the main chipset component (North Bridge or memory controller hub [MCH]). Intel uses the FSB or PSB terminology, whereas AMD uses only FSB. CPU bus is the least confusing of the terms, and it is also completely accurate. Generally speaking, the speed of a processor can be determined by two factors:
In terms of clock speed, the fastest server processors from each manufacturer listed in Tables 2.12.7 and in Chapter 19 include the following in order, from highest to lowest clock speed:
Clock speed figures by themselves can be very misleading. Other factors, including chip architecture, the size of the address bus, single or dual-core design, the presence and size of L2 (and L3) memory cache, the speed of the processor bus, the number of processors installed, and whether the system is using SMP or NUMA multiprocessing also affect server performance. Dual-core designs, which have become very common in the past few years, provide a huge benefit to servers because they provide virtually every benefit of multiple processors, even if the server has room for only one processor. They enable servers to handle more programs and execution threads without slowing down. For example, a single-processor server using a dual-core processor can handle multitasking almost as well as a dual-processor server. A two-way (dual-processor) server becomes the virtual equivalent of a four-way server if dual-core processors are used, and so forth. Although most dual-core processors are slightly lower in clock speed than single-core processors from the same family because of thermal issues, the increased workload, especially in server-oriented tasks, makes a dual-core processor worthwhile. Other portions of the server design, such as system memory speeds and sizes, the speed and interfaces used for network adapters and hard disks, and the operating system used, also affect the actual throughput of a particular server. Because a server provides services to client devices, a server's performance is measured by metrics such as the number of simultaneous clients that can be serviced and the speed at which each client receives information.
How can you determine what processor is installed in a server? If the server is using Windows 2000 Server or Windows Server 2003, you can use SiSoftware Sandra (available from www.sisoftware.co.uk) to determine the processor model, speed, and other information about your system, whether it is running an x86, Alpha, or Itanium processor. To determine basic 64-bit or 32-bit compatibility with Linux or UNIX (RISC) platforms, you can use various command-line options, including the following:
With a MacOS server, you select Apple, About This Mac. Tip To learn more about these commands, see the STATA FAQs "How Can I determine if my computer/OS is 64-bit?" page, at www.stata.com/support/faqs/win/64bit.html. For more detailed information about the processor(s) in your RISC-based server, contact your hardware vendor. The Data I/O BusPerhaps the most important features of a processor are the speed and width of its external data bus. This defines the rate at which data can be moved into or out of the processor, also called the throughput. The processor bus discussed most often is the external data busthe bundle of wires (or pins) used to send and receive data. The more signals that can be sent at the same time, the more data that can be transmitted in a specified interval and, therefore, the faster (and wider) the bus. Having a wider data bus is like having a highway with more lanes, which enables greater throughput. Servers that work with large databases benefit the most from wide data buses. Data in a computer is sent as digital information consisting of a time interval in which a single wire carries a specified voltage to signal a 1 data bit or 0V to signal a 0 data bit. The more wires you have, the more individual bits you can send in the same time interval. A good way to understand this flow of information is to consider a highway and the traffic it carries. If a highway has only one lane for each direction of travel, only one car at a time can move in a certain direction. To increase traffic flow, you can add another lane in each direction so that twice as many cars pass in a specified time. You can think of an 8-bit chip as being a single-lane highway because 1 byte flows through at a time. (1 byte equals 8 individual bits.) The 16-bit chip, with 2 bytes flowing at a time, resembles a two-lane highway. You might have four lanes in each direction to move a large number of automobiles; this structure corresponds to a 32-bit data bus, which has the capability to move 4 bytes of information at a time. Taking this further, a 64-bit data bus is like an 8-lane highway moving data in and out of the chip. All current server processors feature 64-bit (8 bytes wide) data buses. Therefore, they can transfer 64 bits of data at a time to and from the motherboard chipset or system memory. The Address BusThe address bus is the set of wires that carries the addressing information used to describe the memory location to which the data is being sent or from which the data is being retrieved. As with the data bus, each wire in an address bus carries a single bit of information. This single bit is a single digit in the address. The more wires (digits) used in calculating these addresses, the greater the total number of address locations. The size (or width) of the address bus indicates the maximum amount of RAM a chip can address. Figure 2.1 shows how the data, address, and control buses relate to each other. Figure 2.1. How data, address, and control buses connect the processor, memory, and I/O components of a server.
The earlier highway analogy (from the section "The Data I/O Bus") can be used to show how the address bus fits in. If the data bus is the highway, and the size of the data bus is equivalent to the number of lanes, the address bus relates to the house number or street address. The size of the address bus is equivalent to the number of digits in the house address number. For example, if you live on a street in which the address is limited to a two-digit (base 10) number, no more than 100, or 102, distinct addresses (0099) can exist for that street. Add another digit, and the number of available addresses increases to 1,000 (000999), or 103. Computers use the binary (base 2) numbering system, so a two-digit number provides only four unique addresses (00, 01, 10, and 11), calculated as 22. A three-digit number provides only eight addresses (000111), which is 23. For example, Pentium 4 processors use a 36-bit address bus that calculates as a maximum of 236, or 68,719,476,736 bytes (36GB), address locations. Table 2.8 describes the physical memory-addressing capabilities of server processors.
The width of the data bus and the size of the address bus are not dependent on each other, and chip designers can use whatever size they want for each. Usually, however, chips with larger data buses have larger address buses. The sizes of the buses can provide important information about a chip's relative power, measured in two ways: The size of the data bus is an indication of the chip's information-moving capability, and the size of the address bus tells how much memory the chip can handle. As you can see from Table 2.8, more recent server processors generally have larger address buses than older processors. Larger address buses are critical for servers that must handle very large amounts of data, particularly when working with 64-bit operating systems and extremely large data sets. While 32-bit operating systems cannot directly address more than 4GB of RAM in most situations, 64-bit operating systems can address 1TB or more RAM. Internal RegistersThe size of the internal registers indicates how much information the processor can operate on at one time and how it moves data around internally within the chip. This is sometimes also referred to as the internal data bus, to distinguish it from the external data bus, which connects the processor to memory. A register is a holding cell within the processor; for example, the processor can add numbers in two different registers, storing the result in a third register. The register size determines the size of data on which the processor can operate. The register size also describes the type of software or commands and instructions a chip can run. As described in the following sections, server processors fall into two categories: those with 32-bit registers and those with 64-bit registers. 32-Bit ProcessorsInternal registers are often twice the size of the external data bus, which means the chip requires two cycles to fill a register before the register can be operated on. Server processors with a 32-bit register size and 64-bit data bus, such as the Pentium Pro and its many descendents, up through most versions of the Pentium 4 and the AMD Athlon MP, use this design. To enable the data to be processed efficiently, most 32-bit processors use multiple 32-bit pipelines for processing information. (A pipeline is the section of a processor that performs calculations on data.) As a result, recent processors can perform six or more operations per clock cycle. Although 32-bit processors have reached very high clock speeds and process information efficiently, their biggest drawback is the 4GB limit on directly addressable memory. Note As Table 2.8 indicates, many Intel processors use a 36-bit address bus, which translates into 64GB of addressable memory. However, most processors with a 36-bit address bus have 32-bit register sizes, which limits addressable memory to 4GB. How can a 32-bit server support more than 4GB of RAM? Windows 2000 Advanced Server and Windows Server 2003 Enterprise Edition include a translation feature called Physical Address Extension (PAE), which enables the memory above 4GB to be accessed in 4GB blocks up to 16GB. To access memory above 16GB, some database applications such as SQL Server and Oracle use special APIs called Address Windowing Extensions. These workarounds are not necessary with processors that have 64-bit registers. 64-Bit ProcessorsProcessors with a 64-bit register size can work with programs and data that exceed the 4GB limit imposed by 32-bit architecture. Thus, these processors can be more suitable for server use than 32-bit processors in applications that require manipulation of extremely large amounts of data. However, as discussed later in this chapter, there are profound differences in how different 64-bit processor architectures work with existing 32-bit operating systems and programs. If you plan to use a 64-bit server with existing software, you need to carefully consider these differences before you choose a particular processor platform. Current 64-bit server processors include the following: x86-based 64-bit processors (can also run x86 32-bit software at full speed):
EPIC-based 64-bit processors (can also run x86 32-bit software, but not at top speed):
RISC-based 64-bit processors (compatible with 32-bit RISC-based software varies):
As you can see from this list, although x86-compatible server processors with 64-bit capabilities are relatively new, 64-bit capabilities have been available since the mid-1990s in RISC-based processors. Keep in mind that a 64-bit processor can take full advantage of its architecture only when running a 64-bit operating system and 64-bit applications. |