6.5 Use and Function of Sampling Frequency Synchronizers

A sampling frequency synchronizer may be used to lock a digital audio signal to a reference signal. It could also perform the useful function of reclocking distorted remote signals to remove short- term timing errors (jitter). Three main approaches to sampling frequency synchronization are necessary, depending on the operational requirement. Each will be discussed in turn . These are:

Frame alignment : to deal with signals which are of identical sampling frequency but which are more than 25% of a frame period out of phase with the reference.
Buffering : to deal with signals of nominally the same sampling frequency but which are not locked to the same reference and thus drift slightly with relation to each other.
Sampling frequency conversion : to deal with signals whose sampling frequencies differ by a larger amount than implied in (b), such as between 44.1 and 48 kHz, or between consumer and professional systems in which the consumer device's sampling rate is nominally the same as the professional device's but within a large tolerance (see section 6.4 above).

6.5.1 Frame Alignment

It may be necessary to correct for timing errors in signals that are synchronous to the master clock but have travelled long distances. These will have been delayed and so be out of phase with the reference. This is more properly referred to as 'frame alignment' and is only necessary when a signal is more than 25% of a frame period delayed with reference to the sync reference. Propagation delays are not great, however: for example, an AES/EBU signal must travel some 3.7 km down a typical cable before it is delayed by one sample period; thus it is most unlikely that such a situation will arise in real operational environments unless a large static phase error has been introduced in the sample clock of an incoming signal due to it having been cascaded through a number of devices operating in the genlock mode (see section 6.3).

In order to conform to AES recommendations, frame alignment should rephase the signal to bring it within 5% of a frame period compared with the sync reference. Input signals less than 25% adrift are also expected to be brought within this 5% limit at the output, but this is normally performed within the device itself. Reframing of signals more than 25% adrift may be performed within the device, but if not an external reframer would be required.

6.5.2 Buffering

For signals of nominally the same frequency but very slightly adrift it is possible to use a simple buffer store synchronizer, such as those described by Gilchrist ⁷ and also by Parker ⁸ . In this type of synchronizer, a typical block diagram of which is pictured in Figure 6.10, audio samples are written sequentially into successive addresses of a solid state memory configured in the FIFO manner. These samples are read out of the memory a short time later, clocked by the reference signal, the buffer providing a short-term store to accommodate the variation in input and output rates. If the output rate is slightly faster than the input rate then the buffer will gradually become empty and if it is slower than the input rate the buffer will gradually become full, requiring action at some point to avoid losing data or repeating samples because the buffer cannot be infinitely large. At such a time the read address is reset to the mid point of the buffer, resulting in a slight discontinuity in the audio signal. This discontinuity may be arranged to occur within silent passages of the programme, or alternatively a short crossfade may be introduced at the reset point to 'hide' the discontinuity.

Figure 6.10: Block diagram of an example of a simple buffer store synchronizer.

Buffer store synchronizers have the advantage that most of the time the audio signal is copied bit for bit between input and output, with discontinuities only occurring once every so many minutes, depending on the size of the buffer and the discrepancy in input and output sampling rates. The larger the buffer the longer the gaps between buffer resets, or the greater the discrepancy between sampling rates which may be accommodated. The price for using a larger buffer is a longer delay between input and output, and this must be chosen with the operational requirement in mind. Using a buffer store capable of holding 480 samples, for example, a delay of around 5 ms would result, and buffer resets would occur every 8.3 minutes if the sampling frequencys were at the extremes of the AES5 tolerance of 10 ppm.

6.5.3 Sampling Frequency Conversion

For signals whose sampling frequencies differ by too great an amount to be handled by a buffer store synchronizer it will be necessary to employ sampling frequency conversion. This can be used to convert digital interface signals from one rate to another (say from 44.1 to 48 kHz) without passing through the analog domain. Sampling frequency conversion is not truly a transparent process but modern convertors introduce minimal side effects.

The most basic form of sampling frequency conversion involves the translation of samples at one fixed rate to a new fixed rate, related by a simple fractional ratio. Fractional -ratio conversion involves the mathematical interpolation of samples at the new rate based on the values of samples at the old rate. Digital filtering is used to calculate the amplitudes of the new samples such that they are mathematically correct based on the impulse response of original samples, after low-pass filtering with an upper limit of the Nyquist frequency of the original sampling rate. A clock rate common to both sampling frequencies is used to control the interpolation process. Using this method, some output samples will coincide with input samples, but only a limited number of possibilities exist for the interval between input and output samples. Such a process is nominally jitter free.

If the input and output sampling rates have a variable or non-simple relationship, output samples may be required at any interval in between input samples. This requires an interpolator with many more clock phases than for fractional-ratio conversion, the intention being to pick a clock phase which most closely corresponds with the desired output sample instant at which to calculate the necessary coefficient. There will clearly be a timing error, the audible result of which is equivalent to the effect of jitter, and this may be made smaller by increasing the number of possible interpolator phases. If the input sampling rate is continuously varied (as it might be in variable-speed searching or cueing) the position of interpolated samples with relation to original samples must vary also, and this requires real-time calculation of filter phase.

Errors in sampling frequency conversion should be designed so as to result in noise modulation below the noise floor of a 16-bit system and preferably lower. For example, one such convertor is quoted as introducing distortion and noise at -105 dB ref. 1 kHz at 0 dB FS (equivalent to 18-bit noise performance).