29.5 ATM CELL STRUCTURE

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29.5 ATM CELL STRUCTURE

The ATM cell has 53 bytes, containing 5 bytes of header and 48 bytes of information. The advantages of this small and fixed cell size are:

• Cells can be switched more efficiently, leading to high-speed data transfer.

• Since the cell size is fixed, hardware implementation is easier.

• Queuing delay is reduced.

The cell structure for a user-network interface and a network-network interface are given in Figure 29.5 and Figure 29.6, respectively. Note that the generic flow control field is not for network-network interface. The exact application of this field is for further study.

Figure 29.5: ATM cell: user–network interface.

Figure 29.6: ATM cell: network–network interface.

Note 

The size of the cell is small and fixed, so the ATM switches the cells very fast. Moreover, queuing delay is reduced, and hardware implementation is very easy. For these reasons, ATM is an excellent choice for multimedia communications.

VPI (8 bits and 12 bits): Virtual path identifier. It specifies the routing field for the network.

VCI (16 bits and 16 bits): Virtual circuit identifier. It specifies routing to and from the end user.

Payload type: Payload type consists of three bits: P, Q, and R.

The ATM cell contains the following fields: virtual path identifier, virtual circuit identifier, payload type, cell loss priority, header error control, and user information.

The P bit is 0 for user information, 1 for network management/maintenance information.

The Q bit is 0 if there is no congestion, 1 if there is.

The R bit can be used to convey information between users.

CLP: cell loss priority. CLP is set to 0 to indicate high priority and to 1 to indicate less priority. CLP = 0 implies that the cell should be discarded only if there is no other option, and CLP = 1 indicates that the cell can be discarded.

Header error control (8 bits): Header error control (HEC) bits are calculated based on the remaining 32 bits of header using the polynomial x⁸ + x² + x + 1. Since there are 32 data bits and 8 error control bits, error correction is possible.

Using this simple cell structure, ATM achieves fast switching. This fast switching allows support for multimedia services.

The flow chart for detecting errors/rejecting cells is shown in Figure 29.7. If errors are detected in the HEC bits, correction is attempted. If correction is successful, the cell is taken as valid; otherwise cells are discarded. Single-bit errors are corrected, but cells with burst errors are discarded.

Figure 29.7: ATM header error control asgorithm.

Note 

Using the header error control (HEC) bits, single-bit errors can be corrected. If more than one bit is in error, the cell is discarded by the switch.

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