Chapter6.Generating FPGA Hardware

Chapter 6. Generating FPGA Hardware

The preceding two chapters presented a method of programming, using the Impulse C libraries, that emphasizes a streams-oriented approach to application partitioning and that supports parallelism at the system level. This approach supports the concept of coarse-grained parallelism and allows us to abstract away the details of the actual target platform.

In actual practice, however, we need to be aware of the limitations of the target platform (the FPGA and any related IP components, such as embedded soft processors), and we need to understand how to write C code that can be efficiently compiled to either a processor or an FPGA, as appropriate. In this chapter we'll begin that process of understanding by describing the C-to-hardware compilation flow and by describing some of the C programming constraints you will encounter in current-generation tools.

When writing Impulse C processes that will be compiled to hardware using the Impulse C compiler, there are a number of such constraints you must observe, and there are methods of description that will result in better (or worse) results being generated. This chapter describes these constraints and programming methods in a general way; additional details will be presented in later chapters when we explore more specific examples.

As we investigate the processing flow, we will explore, to a limited extent, the hardware that has been generated in the form of hardware description language files.