1. F. Nekoogar. Timing Verification of Application-Specific Circuits (ASICs) . Upper Saddle River, NJ: Prentice Hall PTR, 1999.
2. P. Rashinkar, P. Paterson, and L. Singh. System-on-a-Chip Verification Methodology and Techniques . Norwell, MA: Kluwer Academic Publishers, 2001.
3. Physical Studio/ShowTime Reference Manual . Sequence Design, Inc., 2002.
4. M. J. S. Smith. Application-Specific Integrated Circuits . Reading, MA: Addison-Wesley, 1997.
5. S. Chow, A. B. Kahng, and M. Sarrafzadeh. "Modern Physical Design: Algorithm, Technology, Methodology (Part III)." ICCAD Tutorial, November 2000.
6. Envisia Silicon Ensemble Place and Route , Training Manual, Version 5.3. Cadence Design Systems, Inc.
7. First Encounter , Silicon Perspective Corporation (A Cadence Company) data sheet.
8. ASIC Products Application Notes, Application of Synopsys Physical Compiler in IBM ASIC Methodology , IBM, August 2001.
9. ASIC Products Application Notes, Application of Cadence Envisia PKS in IBM ASIC Methodology . IBM, May 2001.
10. B. Young. Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages . Upper Saddle River, NJ: Prentice Hall PTR, 2001.