5.1. Bus Architecture Overview

As shown in Figure 5-1, internal system buses provide parallel data transfer paths between these key server components:

• Chipset controllers

• Processor

• Cache

• Main memory

• Peripheral buses

Figure 5-1. Typical buses in a server.

Buses are responsible for moving addresses and data between server components. Control signals indicate what the components are to do with the addresses and data they receive.

The number of electrical lines in the bus determines the bus width. Just as the width of a highway limits how much traffic can pass through, the width of the bus limits how much data can transfer at a time.

Bus width is measured in bits. A 16-bit bus transfers 16 bits, or 2 bytes, at a time over 16 wires; a 32-bit bus uses 32 wires to transfer 4 bytes simultaneously, and so on. This bus width limits maximum data transfer between components.

The bus does not initiate the data transfer. The processor and chipset controllers initiate the data requests and accomplish the transfer across the bus.

In some cases, addresses and data travel on separate physical buses: an address bus and a data bus. In other cases, they use the same bus.

When a system uses the same lines for both addressing and data, it is called multiplexing. Multiplexing gives a set of bus lines and bus connections more than one function. A system controller might first assert the bus with a control signal to transfer addresses across 32 lines of a bus, and then reassert a new control signal to use the same 32 bus lines to transfer data.

5.1.1 Address Bus

The address bus has a dual role. First, it is used to transport the source and destination addresses of data to be transmitted on the data bus. To access the data within a device or memory, its address must be placed on the address bus by an initiator, such as the processor, controller, or bus master.

Second, it identifies memory locations generated by the processor, bus masters, or direct memory access (DMA) controller. For a device to move any data, the address bus has to identify the desired target location within a target device where data might reside.

The range of addresses within memory that a single processor can access is known as the address space. The number of lines, or bits, available to the address bus determines the address space. The size of the address space is calculated by raising the number 2, which is binary with each line or bit being a 0 or 1, to the exponent n: 2n. The exponent n is the number of lines in the address bus, which is the same as the size in bits of the address bus.

Example

An Intel Pentium processor has 32 address lines, which provides 232 addresses or 4GB of address space.

The widths of the address bus and maximum addressable memory for the Intel processor family are listed in the following table.

Processor	Address Lines (Bits)	Theoretical Maximum Addressable Memory
8086	20	1MB
80286	24	16MB
80386 and 80486	32	4GB
Pentium	32	4GB
Pentium Pro	36	64GB
Pentium II, III, and 4	36	64GB
Pentium II Xeon and III Xeon	36	64GB
Xeon	36	64GB
Itanium	64	264 GB

Note

The ability of the processor to access the maximum address space can be restricted by the chipsets and the operating system.

5.1.2 Data Bus

The data bus is the internal pathway that carries data to and from the processor or to and from memory. Data moves between any two devices over the data bus. The data can be instructions for the processor or information the processor is transmitting. This information can pass to or from the memory or I/O subsystem.

The width and speed of the data bus directly affect performance and significantly influence system throughput. The bus width is the number of lines or wires that make up the bus. Each line or wire of a data bus can carry 1 bit of information.

The width of the bus is equal to the number of data pins on the processor or other device. Data buses are designed in multiples of eight lines because each line carries 1 bit of data and 8 bits make up a byte. Therefore, the data bus width indicates how many bytes the bus can carry during each transfer. A 32-bit bus can transmit 4 bytes at one time; a 64-bit bus can transfer 8 bytes per cycle.

The following table shows the width of the data bus for various Intel processors.

Processor	Data Bus Width
8086 and 80286	16 bits
80386 and 80486	32 bits
Pentium and Pentium Pro	64 bits
Pentium II, III, and 4	64 bits
Pentium II Xeon and III Xeon	64 bits
Itanium	64 bits

5.1.3 Control Signals

Control signals usually travel on the address bus. The signals determine the actions of the addressed components. (Control signals are sometimes referred to as the control bus even though they are not a separate physical bus.)

Control signals have three primary functions:

• Device arbitration The control signal identifies which device has control of the bus and prevents collisions.

• Data-flow direction The control signal identifies the direction of the bus cycle, read or write, and indicates when the cycle is complete.

• Memory addressing type The control signal identifies whether the operation being performed is for memory or I/O.

Some control signal notations generated by the processor or other device include the following:

• W/R Write/read

• IRQ Interrupt requests

• BCLK Bus clock

• DRQ DMA requests

Many of these signals are point to point. Point-to-point signaling is intended for only one device on a dedicated line.