What are the two main performance bottlenecks in the original PC chipset?
3:
What was the main benefit of the dual independent bus architecture? Where was the bottleneck with this architecture?
4:
What server subsystem was the point of contention with bus mastering technology?
5:
What were the three main functions of the memory and I/O (MIOC) technology?
6:
Which system architecture first provided peripherals with independent access to processors and memory?
7:
Which architecture provided dual-peer PCI buses and employed dual memory controllers that processed memory requests in parallel?
8:
What innovation enabled each of the five main ports to transfer data at high speed to each of the other ports, allowing concurrent read/writes between processors, memory, and I/O?
9:
What chipset uses a two-port (bus) memory design with 1.6GB/s memory bandwidth (2 x 800MB/s), allowing simultaneous access to memory on both ports?
10:
What three advantages does the F8 chipset have over the NUMA architecture?
